An FPGA Hardware Parallel Implementation of the DES Algorithm. - I. N. Tselepis; Michael P. Bekakos (Neural Parallel Sci. Comput., 2004)

Computing all-pairs shortest paths on a linear systolic array and hardware realization on a reprogrammable FPGA platform. - Emina I. Milovanovic; Igor Z. Milovanovic; Michael P. Bekakos; I. N. Tselepis (J. Supercomput., 2007)

Forty-three ways of systolic matrix multiplication. - Igor Z. Milovanovic; Michael P. Bekakos; I. N. Tselepis; Emina I. Milovanovic (Int. J. Comput. Math., 2010)