An efficient three-point arc algorithm. - Ian Galton (IEEE Computer Graphics and Applications, 1989)

One-bit Dithering in Delta-Sigma Modulator-based D/A Conversion. - Ian Galton (ISCAS, 1993)

Combined RF Phase Extraction and Digitalization. - Ian Galton; George Zimmerman (ISCAS, 1993)

Granular quantization noise in the first-order delta-sigma modulator. - Ian Galton (IEEE Trans. Inf. Theory, 1993)

Higher-Order Delta-Sigma Frequency to Digital Conversion. - Ian Galton (ISCAS, 1994)

Granular quantization noise in a class of delta-sigma modulators. - Ian Galton (IEEE Trans. Inf. Theory, 1994)

A Practical Second-Order Delta-Digma Frequency-to-Digital Converter. - Ian Galton (ISCAS, 1995)

A Robust Parallel Delta-Sigma A/D Converter Architecture. - Henrik T. Jensen 001; Ian Galton (ISCAS, 1995)

A delta-sigma PLL for 14-b, 50 kSample/s frequency-to-digital conversion of a 10 MHz FM signal. - Ian Galton; William Huff; Paolo Carbone; Eric Siragusa (IEEE J. Solid State Circuits, 1998)

A Nyquist-rate delta-sigma A/D converter. - Eric T. King; Aria Eshraghi; Ian Galton; Terri S. Fiez (IEEE J. Solid State Circuits, 1998)

A 3.3 V single-poly CMOS audio ADC delta-sigma modulator with 98 dB peak SINAD. - Eric Fogleman; Ian Galton; William Huff; Henrik Jensen 001 (CICC, 1999)

An area-efficient differential input ADC with digital common mode rejection. - Eric Fogleman; Ian Galton; Henrik Jensen 001 (ISCAS (2), 1999)

A dynamic element matching technique for reduced-distortion multibit quantization in delta-sigma ADCs. - Eric Fogleman; Ian Galton; Henrik Jensen 001 (ISCAS (2), 1999)

An audio ADC delta-sigma modulator with 100 dB SINAD and 102 dB DR using a second-order mismatch-shaping DAC. - Eric Fogleman; Jared Welz; Ian Galton (CICC, 2000)

A 3.3-V single-poly CMOS audio ADC delta-sigma modulator with 98-dB peak SINAD and 105-dB peak SFDR. - Eric Fogleman; Ian Galton; William Huff; Henrik Jensen 001 (IEEE J. Solid State Circuits, 2000)

The mismatch-noise PSD from a tree-structured DAC in a second-order ΔΣ modulator with a midscale input. - Jared Welz; Ian Galton (ICASSP, 2001)

An audio ADC Delta-Sigma modulator with 100-dB peak SINAD and 102-dB DR using a second-order mismatch-shaping DAC. - Eric Fogleman; Jared Welz; Ian Galton (IEEE J. Solid State Circuits, 2001)

Segmented mismatch-shaping D/A conversion. - Asaf Fishov; Eric Siragusa; Jared Welz; Eric Fogleman; Ian Galton (ISCAS (4), 2002)

A necessary and sufficient condition for mismatch shaping in multi-bit DACs. - Jared Welz; Ian Galton (ISCAS (1), 2002)

A 12-mW ADC delta-sigma modulator with 80 dB of dynamic range integrated in a single-chip Bluetooth transceiver. - Jorge Grilo; Ian Galton; Kevin J. Wang; Raymond Montemayor (IEEE J. Solid State Circuits, 2002)

A multiple-crystal interface PLL with VCO realignment to reduce phase noise. - Sheng Ye; Lars C. Jansson; Ian Galton (IEEE J. Solid State Circuits, 2002)

Techniques for in-band phase noise suppression in re-circulating DLLs. - Sheng Ye; Lars C. Jansson; Ian Galton (CICC, 2003)

Editorial. - Ian Galton (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

Phase-noise cancellation design tradeoffs in delta-sigma fractional-N PLLs. - Sudhakar Pamarti; Ian Galton (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation. - Sudhakar Pamarti; Lars C. Jansson; Ian Galton (IEEE J. Solid State Circuits, 2004)

A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC. - Eric Siragusa; Ian Galton (IEEE J. Solid State Circuits, 2004)

Techniques for phase noise suppression in recirculating DLLs. - Sheng Ye; Ian Galton (IEEE J. Solid State Circuits, 2004)

A tight signal-band power bound on mismatch noise in a mismatch-shaping digital-to-analog converter. - Jared Welz; Ian Galton (IEEE Trans. Inf. Theory, 2004)

Addition to "A Wideband 2.4-GHz Delta-Sigma Fractional-$N$PLL With 1-Mb/s In-Loop Modulation". - Sudhakar Pamarti; Lars C. Jansson; Ian Galton (IEEE J. Solid State Circuits, 2005)

A 14b 100MS/s DAC with Fully Segmented Dynamic Element Matching. - Kok Lim Chan; Ian Galton (ISSCC, 2006)

Digital Background Correction of Harmonic Distortion in Pipelined ADCs. - Andrea Panigada; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

Analog, Mixed-Signal, and RF Circuit Design in Nanometer CMOS. - Ian Galton; Matt Miller; Robert Bogdan Staszewski; Bram Nauta; Michiel Steyaert (ISSCC, 2007)

A Wide-Bandwidth 2.4GHz ISM-Band Fractional-N PLL with Adaptive Phase-Noise Cancellation. - Ashok Swaminathan; Kevin J. Wang; Ian Galton (ISSCC, 2007)

A Wide-Bandwidth 2.4 GHz ISM Band Fractional-N PLL With Adaptive Phase Noise Cancellation. - Ashok Swaminathan; Kevin J. Wang; Ian Galton (IEEE J. Solid State Circuits, 2007)

LSB Dithering in MASH Delta-Sigma D/A Converters. - Sudhakar Pamarti; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta-Sigma Modulators. - Sudhakar Pamarti; Jared Welz; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

A Digital Requantizer With Shaped Requantization Noise That Remains Well Behaved After Nonlinear Distortion. - Ashok Swaminathan; Andrea Panigada; Elias Masry; Ian Galton (IEEE Trans. Signal Process., 2007)

Short Course. - Ian Galton; Jonathan Audy; Vadim Ivanov; Stefan Rusu; Seth R. Sanders (ISSCC, 2008)

Spurious -Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4GHz Fractional-N PLL. - Kevin J. Wang; Ashok Swaminathan; Ian Galton (ISSCC, 2008)

Dynamic Element Matching to Prevent Nonlinear Distortion From Pulse-Shape Mismatches in High-Resolution DACs. - Kok Lim Chan; Jianyu Zhu; Ian Galton (IEEE J. Solid State Circuits, 2008)

Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL. - Kevin J. Wang; Ashok Swaminathan; Ian Galton (IEEE J. Solid State Circuits, 2008)

Segmented Dynamic Element Matching for High-Resolution Digital-to-Analog Conversion. - Kok Lim Chan; Nevena Rakuljic; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

Low-voltage analog and mixed-signal CMOS circuit design. - Ian Galton (ISSCC, 2009)

A 130mW 100MS/s pipelined ADC with 69dB SNDR enabled by digital harmonic distortion correction. - Andrea Panigada; Ian Galton (ISSCC, 2009)

A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction. - Andrea Panigada; Ian Galton (IEEE J. Solid State Circuits, 2009)

CMOS phase-locked loops for frequency synthesis. - Ian Galton; Behzad Razavi; John Cowles; Peter R. Kinget (ISSCC, 2010)

A mostly digital variable-rate continuous-time ADC ΔΣ modulator. - Gerry Taylor; Ian Galton (ISSCC, 2010)

A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC. - Gerry Taylor; Ian Galton (IEEE J. Solid State Circuits, 2010)

Why Dynamic-Element-Matching DACs Work. - Ian Galton (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Tree-Structured DEM DACs with Arbitrary Numbers of Levels. - Nevena Rakuljic; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Correction to "A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC" [Nov 10 2250-2261]. - Gerry Taylor; Ian Galton (IEEE J. Solid State Circuits, 2011)

A Discrete-Time Model for the Design of Type-II PLLs With Passive Sampled Loop Filters. - Kevin J. Wang; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

A reconfigurable mostly-digital ΔΣ ADC with a worst-case FOM of 160dB. - Gerry Taylor; Ian Galton (VLSIC, 2012)

A Reconfigurable Mostly-Digital Delta-Sigma ADC With a Worst-Case FOM of 160 dB. - Gerry Taylor; Ian Galton (IEEE J. Solid State Circuits, 2013)

Suppression of Quantization-Induced Convergence Error in Pipelined ADCs With Harmonic Distortion Correction. - Nevena Rakuljic; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Delta-Sigma FDC Based Fractional-N PLLs. - Christian Venerus; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A Fundamental Limitation of DC-Free Quantization Noise With Respect To Nonlinearity-Induced Spurious Tones. - Eythan Familier; Ian Galton (IEEE Trans. Signal Process., 2013)

A Class of Quantizers With DC-Free Quantization Noise and Optimal Immunity to Nonlinearity-Induced Spurious Tones. - Eythan Familier; Christian Venerus; Ian Galton (IEEE Trans. Signal Process., 2013)

25.1 A highly-digital frequency synthesizer using ring-oscillator frequency-to-digital conversion and noise cancellation. - Colin Weltin-Wu; Guobi Zhao; Ian Galton (ISSCC, 2015)

A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8-3.5 GHz DCO. - Christian Venerus; Ian Galton (IEEE J. Solid State Circuits, 2015)

Errata for "A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8-3.5 GHz DCO". - Christian Venerus; Ian Galton (IEEE J. Solid State Circuits, 2015)

A 3.5 GHz Digital Fractional-N PLL Frequency Synthesizer Based on Ring Oscillator Frequency-to-Digital Conversion. - Colin Weltin-Wu; Guobi Zhao; Ian Galton (IEEE J. Solid State Circuits, 2015)

Quantization Noise Cancellation for FDC-Based Fractional-N PLLs. - Christian Venerus; Ian Galton (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A Linearized Model for the Design of Fractional-N Digital PLLs Based on Dual-Mode Ring Oscillator FDCs. - Colin Weltin-Wu; Eythan Familier; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Second and Third-Order Noise Shaping Digital Quantizers for Low Phase Noise and Nonlinearity-Induced Spurious Tones in Fractional-N PLLs. - Eythan Familier; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Simplified Logic for Tree-Structure Segmented DEM Encoders. - Christian Venerus; Jason Remple; Ian Galton (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Second and third-order successive requantizers for spurious tone reduction in low-noise fractional-N PLLs. - Eythan Familier; Ian Galton (CICC, 2017)

The Effects of Inter-Symbol Interference in Dynamic Element Matching DACs. - Jason Remple; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Multi-Rate DEM With Mismatch-Noise Cancellation for DCOs in Digital PLLs. - Enrique Alvarez-Fontecilla; Christian Venerus; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Adaptive Cancellation of Static and Dynamic Mismatch Error in Continuous-Time DACs. - Derui Kong; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS. - Austin Rovinski; Chun Zhao; Khalid Al-Hawaj; Paul Gao 001; Shaolin Xie; Christopher Torng; Scott Davidson 004; Aporva Amarnath; Luis Vega; Bandhav Veluri; Anuj Rao; Tutu Ajayi; et al. (VLSI Circuits, 2019)

A 600-MS/s DAC With Over 87-dB SFDR and 77-dB Peak SNDR Enabled by Adaptive Cancellation of Static and Dynamic Mismatch Error. - Derui Kong; Kevin Rivas-Rivera; Ian Galton (IEEE J. Solid State Circuits, 2019)

Understanding Phase Error and Jitter: Definitions, Implications, Simulations, and Measurement. - Ian Galton; Colin Weltin-Wu (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Subsampling Mismatch Noise Cancellation for High-Speed Continuous-Time DACs. - Derui Kong; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

MSE Analysis of a Multi-Loop LMS Pseudo-Random Noise Canceler for Mixed-Signal Circuit Calibration. - Derui Kong; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Spectral Breathing and Its Mitigation in Digital Fractional-N PLLs. - Enrique Alvarez-Fontecilla; Eslam Helal; Amr I. Eissa; Ian Galton (IEEE J. Solid State Circuits, 2021)

A Time Amplifier Assisted Frequency-to-Digital Converter Based Digital Fractional-N PLL. - Eslam Helal; Enrique Alvarez-Fontecilla; Amr I. Eissa; Ian Galton (IEEE J. Solid State Circuits, 2021)

Delta-Sigma FDC Enhancements for FDC-Based Digital Fractional-N PLLs. - Enrique Alvarez-Fontecilla; Amr I. Eissa; Eslam Helal; Colin Weltin-Wu; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

An ISI Scrambling Technique for Dynamic Element Matching Current-Steering DACs. - Jason Remple; Andrea Panigada; Ian Galton (IEEE J. Solid State Circuits, 2022)

DTC Linearization via Mismatch-Noise Cancellation for Digital Fractional-N PLLs. - Eslam Helal; Amr I. Eissa; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Adaptive Cancellation of Inter-Symbol Interference in High-Speed Continuous-Time DACs. - Subin Kim; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 2.5-20kSps in-Pixel Direct Digitization Front-End for ECoG with In-Stimulation Recording. - Aditi Jain; Eric Fogleman; Paul Botros; Ritwik Vatsyayan; Corentin Pochet; Andrew M. Bourhis; Zhaoyi Liu; Suhas Chethan; Hanh-Phuc Le; Ian Galton; Shadi A. Dayeh; Drew A. Hall (CICC, 2024)

A Duty-Cycle-Error-Immune Reference Frequency Doubling Technique for Fractional-N Digital PLLs. - Amr I. Eissa; Enrique Alvarez-Fontecilla; Colin Weltin-Wu; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A Scalable 256-Channel 12-mA 0.06%-Current-Mismatch 22-V Neurostimulator with Real-Time Current Calibration and Compliance Monitoring. - Po-Han Chen; Zhiheng Luo; Spencer Chang; Kristopher Ngo; Ritwik Vatsyayan; Jihwan Lee; Tara Porter; Drew A. Hall; Shadi A. Dayeh; Ian Galton; Hanh-Phuc Le (CICC, 2025)

A 2.5-20 kS/s In-Pixel Direct Digitization ECoG Front End With Submillisecond Stimulation Artifact Recovery. - Aditi Jain; Eric Fogleman; Paul Botros; Ritwik Vatsyayan; Asish Koruprolu; Corentin Pochet; Andrew M. Bourhis; Zhaoyi Liu; Suhas Chethan; Hanh-Phuc Le; Ian Galton; Shadi A. Dayeh; et al. (IEEE J. Solid State Circuits, 2025)

Enhanced ISI Analysis and Fast Circuit Simulation of High-Speed Current-Steering DACs. - Subin Kim; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)