Automated design of switched-current cells. - Ian O'Connor; Andreas Kaiser (CICC, 1998)

Design and Optimization of Optical Links Based on VHDL-AMS Modeling. - Pascal Bontoux; Fabien Mieyeville; Ian O'Connor; Frédéric Gaffiot; Gilles Jacquemod (BMAS, 2000)

An analog beam-forming circuit for ultrasound imaging using switched-current delay lines. - Bruno Stefanelli; Ian O'Connor; Laurent Quiquerez; Andreas Kaiser; Daniel Billet (IEEE J. Solid State Circuits, 2000)

Automated synthesis of current-memory cells. - Ian O'Connor; Andreas Kaiser (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

A VHDL-AMS library of hierarchical optoelectronic device models. - Fabien Mieyeville; Matthieu Briere; Ian O'Connor; Frédéric Gaffiot; Gilles Jacquemod (FDL, 2003)

Hierarchical synthesis of high-speed CMOS photoreceiver front-ends using a multi-domain behavioural description language. - Faress Tissafi-Drissi; Ian O'Connor; Fabien Mieyeville; Frédéric Gaffiot (FDL, 2003)

Predictive design space exploration of maximum bandwidth CMOS photoreceiver preamplifiers. - Ian O'Connor; Fabien Mieyeville; Faress Tissafi-Drissi; Grzegorz Tosik; Frédéric Gaffiot (ICECS, 2003)

Optical versus Electrical Interconnections for Clock Distribution Networks in New VLSI Technologies. - Grzegorz Tosik; Frédéric Gaffiot; Zbigniew Lisik; Ian O'Connor; Faress Tissafi-Drissi (PATMOS, 2003)

Design Methodologies for High-Speed CMOS Photoreceiver Front-Ends. - Faress Tissafi-Drissi; Ian O'Connor; Fabien Mieyeville; Frédéric Gaffiot (SBCCI, 2003)

On-Chip Optical Interconnect for Low-Power. - Ian O'Connor; Frédéric Gaffiot (Ultra Low-Power Electronics and Design, 2004)

Design and Behavioral Modeling Tools for Optical Network-on-Chip. - Matthieu Briere; Laurent Carrel; T. Michalke; Fabien Mieyeville; Ian O'Connor; Frédéric Gaffiot (DATE, 2004)

Extremely Low-Power Logic. - Christian Piguet; Jacques Gautier; Christoph Heer; Ian O'Connor; Ulf Schlichtmann (DATE, 2004)

RUNE: Platform for Automated Design of Integrated Multi-Domain Systems. Application to High-Speed CMOS Photoreceiver Front-Ends. - Faress Tissafi-Drissi; Ian O'Connor; Frédéric Gaffiot (DATE, 2004)

Optical Network On-chip Multi-Domain modeling using SystemC. - Emmanuel Drouard; Matthieu Briere; Fabien Mieyeville; Ian O'Connor; Xavier Letartre (FDL, 2004)

Simulation of Electrical and Optical Interconnections for Future VLSI ICs. - Grzegorz Tosik; Zbigniew Lisik; Malgorzata Langer; Frédéric Gaffiot; Ian O'Connor (International Conference on Computational Science, 2004)

Optical solutions for system-level interconnect. - Ian O'Connor (SLIP, 2004)

VHDL & VHDL-AMS Modelling and Simulation of a CMOS Imager IP. - David Navarro; D. Ramat; Fabien Mieyeville; Ian O'Connor; Frédéric Gaffiot; Laurent Carrel (FDL, 2005)

UML/XML based approach to hierarchical AMS Synthesis. - Ian O'Connor; Faress Tissafi-Drissi; G. Revy; Frédéric Gaffiot (FDL, 2005)

Towards reconfigurable optical networks on chip. - Ian O'Connor; Matthieu Briere; Emmanuel Drouard; Art Kazmierczak; Faress Tissafi-Drissi; David Navarro; Fabien Mieyeville; Joni Dambre; Dirk Stroobandt; Jean-Marc Fedeli; Zbigniew Lisik; Frédéric Gaffiot (ReCoSoC, 2005)

Heterogeneous Modelling of an Optical Network-on-Chip with SystemC. - Matthieu Briere; Emmanuel Drouard; Fabien Mieyeville; David Navarro; Ian O'Connor; Frédéric Gaffiot (IEEE International Workshop on Rapid System Prototyping, 2005)

Novel CNTFET-based Reconfigurable Logic Gate Design. - Junchen Liu; Ian O'Connor; David Navarro; Frédéric Gaffiot (DAC, 2007)

System level assessment of an optical NoC in an MPSoC platform. - Matthieu Briere; Bruno Girodias; Youcef Bouchebaba; Gabriela Nicolescu; Fabien Mieyeville; Frédéric Gaffiot; Ian O'Connor (DATE, 2007)

Heterogeneous systems on chip and systems in package. - Ian O'Connor; Bernard Courtois; Krishnendu Chakrabarty; N. Delorme; M. Hampton; J. Hartung (DATE, 2007)

Towards the High-Level Design of Optical Networks-on-Chip. Formalization of Opto-Electrical Interfaces. - Matthieu Briere; Luiza Gheorghe; Gabriela Nicolescu; Ian O'Connor; Gabriel A. Wainer (ICECS, 2007)

Ultra-fine grain reconfigurability using CNTFETs. - Ian O'Connor; Junchen Liu; David Navarro; Ilham Hassoune; Stéphane Burignat; Frédéric Gaffiot (ICECS, 2007)

Design of a Novel CNTFET-based Reconfigurable Logic Gate. - Junchen Liu; Ian O'Connor; David Navarro; Frédéric Gaffiot (ISVLSI, 2007)

A Family of Ultra-Fine Grain CNTFET-based Reconfigurable Logic Gates. - Junchen Liu; Ian O'Connor; David Navarro; Frédéric Gaffiot (ReCoSoC, 2007)

CNTFET Modeling and Reconfigurable Logic-Circuit Design. - Ian O'Connor; Junchen Liu; Frédéric Gaffiot; Fabien Prégaldiny; Christophe Lallement; Cristell Maneux; Johnny Goguet; Sébastien Fregonese; Thomas Zimmer; Lorena Anghel; Trong-Trinh Dang; Régis Leveugle (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Systematic Simulation-Based Predictive Synthesis of Integrated Optical Interconnect. - Ian O'Connor; Faress Tissafi-Drissi; Frédéric Gaffiot; Joni Dambre; Michiel De Wilde; Jan Van Campenhout; Dries Van Thourhout; Dirk Stroobandt (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Fine-Grain Reconfigurable Logic Cells Based on Double-Gate MOSFETs. - Ian O'Connor; Ilham Hassoune; David Navarro (VLSI-SoC (Selected Papers), 2008)

Piecewise-polynomial modeling for analog circuit performance metrics. - Hubert Filiol; Ian O'Connor; Dominique Morche (ECCTD, 2009)

Optical NoC design-parameters exploration and analysis. - Atef Allam; Ian O'Connor; Emmanuel Drouard; Fabien Mieyeville; Alberto Scandurra (ICECS, 2009)

Reconfigurable nanoscale logic cells : a comparison study. - Pierre-Emmanuel Gaillardon; Fabien Clermidy; Ian O'Connor; Renaud Daviot (ICECS, 2009)

Mapping method of reconfigurable cell matrices based on nanoscale devices using inter-stage fixed interconnection scheme. - Pierre-Emmanuel Gaillardon; Fabien Clermidy; Ian O'Connor; Junchen Liu; Renaud Daviot (ICECS, 2009)

Interconnection scheme and associated mapping method of reconfigurable cell matrices based on nanoscale devices. - Pierre-Emmanuel Gaillardon; Fabien Clermidy; Ian O'Connor; Junchen Liu (NANOARCH, 2009)

Emerging Technologies and Nanoscale Computing Fabrics. - Ian O'Connor; Junchen Liu; Kotb Jabeur; Nataliya Yakymets; Renaud Daviot; David Navarro; Pierre-Emmanuel Gaillardon; Fabien Clermidy; Maimouna Amadou; Gabriela Nicolescu (VLSI-SoC, 2009)

Modeling and Formal Verification of a Passive Optical Network on Chip Behavior. - Luiza Gheorghe Iugan; Gabriela Nicolescu; Ian O'Connor (Electron. Commun. Eur. Assoc. Softw. Sci. Technol., 2009)

Bottom-up Verification Methodology for CMOS Photonic Linear Heterogeneous System. - Bo Wang; Ian O'Connor; Emmanuel Drouard; Lioua Labrak (FDL, 2010)

Phase-change-memory-based storage elements for configurable logic. - Pierre-Emmanuel Gaillardon; M. Haykel Ben Jamaa; Marina Reyboz; Giovanni Beneventi; Fabien Clermidy; Luca Perniola; Ian O'Connor (FPT, 2010)

Logic cells and interconnect strategies for nanoscale reconfigurable computing fabrics. - Ian O'Connor; Kotb Jabeur; David Navarro; Nataliya Yakymets; Pierre-Emmanuel Gaillardon; M. Haykel Ben Jamaa; Fabien Clermidy (ICECS, 2010)

Optical network-on-chip reconfigurable model for multi-level analysis. - Atef Allam; Ian O'Connor; Alberto Scandurra (ISCAS, 2010)

Reducing transistor count in clocked standard cells with ambipolar double-gate FETs. - Kotb Jabeur; David Navarro; Ian O'Connor; Pierre-Emmanuel Gaillardon; M. Haykel Ben Jamaa; Fabien Clermidy (NANOARCH, 2010)

Performance evaluation for passive-type Optical network-on-chip. - Atef Allam; Ian O'Connor; Wim Heirman (International Symposium on Rapid System Prototyping, 2010)

Multi-Optical Network-on-Chip for Large Scale MPSoC. - Sébastien Le Beux; Jelena Trajkovic; Ian O'Connor; Gabriela Nicolescu; Guy Bois; Pierre G. Paulin (IEEE Embed. Syst. Lett., 2010)

ULPFA: A New Efficient Design of a Power-Aware Full Adder. - Ilham Hassoune; Denis Flandre; Ian O'Connor; Jean-Didier Legat (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Can we go towards true 3-D architectures? - Pierre-Emmanuel Gaillardon; M. Haykel Ben Jamaa; Paul-Henry Morel; Jean-Philippe Noël; Fabien Clermidy; Ian O'Connor (DAC, 2011)

Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology. - Sébastien Le Beux; Jelena Trajkovic; Ian O'Connor; Gabriela Nicolescu; Guy Bois; Pierre G. Paulin (DATE, 2011)

Multi-granularity thermal evaluation of 3D MPSoC architectures. - Alain Fourmigue; Giovanni Beltrame; Gabriela Nicolescu; El Mostapha Aboulhamid; Ian O'Connor (DATE, 2011)

Fine-grain reconfigurable logic cells based on double-gate CNTFETs. - Kotb Jabeur; Nataliya Yakymets; Ian O'Connor; Sébastien Le Beux (ACM Great Lakes Symposium on VLSI, 2011)

High performance 4: 1 multiplexer with ambipolar double-gate FETs. - Kotb Jabeur; Ian O'Connor; Nataliya Yakymets; Sébastien Le Beux (ICECS, 2011)

Evaluation of a crossbar multiplexer in a lithography-based nanowire technology. - Pierre-Emmanuel Gaillardon; M. Haykel Ben Jamaa; Fabien Clermidy; Ian O'Connor (ISCAS, 2011)

IDEA1: A Validated System C-Based Simulator for Wireless Sensor Networks. - Wan Du; David Navarro; Fabien Mieyeville; Ian O'Connor (MASS, 2011)

Ultra-fine grain FPGAs: A granularity study. - Pierre-Emmanuel Gaillardon; M. Haykel Ben Jamaa; Fabien Clermidy; Ian O'Connor (NANOARCH, 2011)

Ambipolar double-gate FET binary-decision- diagram (Am-BDD) for reconfigurable logic cells. - Kotb Jabeur; Nataliya Yakymets; Ian O'Connor; Sébastien Le Beux (NANOARCH, 2011)

Using Self-Reconfiguration to Increase Manufacturing Yield of CNTFET-based Architectures. - Hui Zhu; Sébastien Le Beux; Nataliya Yakymets; Ian O'Connor (ReConFig, 2011)

Multi-objective mapping for matrix-based nanocomputer architectures. - Nataliya Yakymets; Sébastien Le Beux; Kotb Jabeur; Ian O'Connor (ReCoSoC, 2011)

Layout guidelines for 3D architectures including Optical Ring Network-on-Chip (ORNoC). - Sébastien Le Beux; Jelena Trajkovic; Ian O'Connor; Gabriela Nicolescu (VLSI-SoC, 2011)

3D-IC floorplanning: Applying meta-optimization to improve performance. - Felipe Frantz; Lioua Labrak; Ian O'Connor (VLSI-SoC, 2011)

Reprogramming hardware-software heterogeneous Wireless Sensor Networks. - Mihai Galos; Fabien Mieyeville; David Navarro; Ian O'Connor (WPMC, 2011)

IDEA1: A validated SystemC-based system-level design and simulation environment for wireless sensor networks. - Wan Du; Fabien Mieyeville; David Navarro; Ian O'Connor (EURASIP J. Wirel. Commun. Netw., 2011)

Matrix Nanodevice-Based Logic Architectures and Associated Functional Mapping Method. - Pierre-Emmanuel Gaillardon; Fabien Clermidy; Ian O'Connor; Junchen Liu; Maimouna Amadou; Gabriela Nicolescu (ACM J. Emerg. Technol. Comput. Syst., 2011)

Ambipolar double-gate FETs for the design of compact logic structures. - Kotb Jabeur; Ian O'Connor; Nataliya Yakymets; Sébastien Le Beux (ACM Great Lakes Symposium on VLSI, 2012)

Wavelength division multiplexed photonic layer on CMOS. - Ian O'Connor; Dries Van Thourhout; Alberto Scandurra (INA-OCMC@HiPEAC, 2012)

Ambipolar double gate CNTFETs based reconfigurable logic cells. - Kotb Jabeur; Ian O'Connor; Sébastien Le Beux; David Navarro (NANOARCH, 2012)

Low-power design technique with ambipolar double gate devices. - Kotb Jabeur; Ian O'Connor; David Navarro; Sébastien Le Beux (NANOARCH, 2012)

Ambipolar independent double gate FET logic. - Ian O'Connor; Kotb Jabeur; Sébastien Le Beux; David Navarro (NANOARCH, 2012)

A cycle-accurate transaction-level modelled energy simulation approach for heterogeneous Wireless Sensor Networks. - Mihai Galos; David Navarro; Fabien Mieyeville; Ian O'Connor (NEWCAS, 2012)

3D IC floorplanning: Automating optimization settings and exploring new thermal-aware management techniques. - Felipe Frantz; Lioua Labrak; Ian O'Connor (Microelectron. J., 2012)

Analog IC Variability Bound Estimation Using the Cornish-Fisher Expansion. - Hubert Filiol; Ian O'Connor; Dominique Morche (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Optical look up table. - Zhen Li 046; Sébastien Le Beux; Christelle Monat; Xavier Letartre; Ian O'Connor (DATE, 2013)

Energy Measurements and Evaluations on High Data Rate and Ultra Low Power WSN Node. - Nanhao Zhu; Ian O'Connor (ICNSC, 2013)

Potential and pitfalls of silicon photonics computing and interconnect. - Sébastien Le Beux; Ian O'Connor; Zhen Li 046; Xavier Letartre; Christelle Monat; Jelena Trajkovic; Gabriela Nicolescu (ISCAS, 2013)

Performance evaluations of unslotted CSMA/CA algorithm at high data rate WSNs scenario. - Nanhao Zhu; Ian O'Connor (IWCMC, 2013)

Energy Performance of High Data Rate and Low Power Transceiver based Wireless Body Area Networks. - Nanhao Zhu; Ian O'Connor (SENSORNETS, 2013)

Reconfigurable photonic switching: Towards all-optical FPGAs. - Sébastien Le Beux; Zhen Li 046; Christelle Monat; Xavier Letartre; Ian O'Connor (VLSI-SoC, 2013)

iMASKO: A Genetic Algorithm Based Optimization Framework for Wireless Sensor Networks. - Nanhao Zhu; Ian O'Connor (J. Sens. Actuator Networks, 2013)

Reduction methods for adapting optical network on chip topologies to 3D architectures. - Sébastien Le Beux; Ian O'Connor; Gabriela Nicolescu; Guy Bois; Pierre G. Paulin (Microprocess. Microsystems, 2013)

Functions classification approach to generate reconfigurable fine-grain logic based on Ambipolar Independent Double Gate FET (Am-IDGFET). - Kotb Jabeur; Ian O'Connor; Nataliya Yakymets (Microelectron. J., 2013)

Chameleon: Channel efficient Optical Network-on-Chip. - Sébastien Le Beux; Hui Li 034; Ian O'Connor; Kazem Cheshmi; Xuchen Liu; Jelena Trajkovic; Gabriela Nicolescu (DATE, 2014)

Hierarchical design flow for heterogenous systems using Pareto front interpolation. - Lioua Labrak; Ian O'Connor; Felipe Frantz (ICECS, 2014)

A reconfigurable optical network on chip for streaming applications. - Sébastien Le Beux; Hui Li 034; Gabriela Nicolescu; Ian O'Connor (ReCoSoC, 2014)

Silicon photonics design rule checking: Application of a programmable modeling engine for non-Manhattan geometry verification. - Ruping Cao; John Ferguson; Fabien Gays; Youssef Drissi; Alexandre Arriordaz; Ian O'Connor (VLSI-SoC, 2014)

Complementary logic interface for high performan optical computing with OLUT. - Zhen Li 046; Sébastien Le Beux; Ian O'Connor; Christelle Monat; Xavier Letartre (VLSI-SoC, 2014)

Optical crossbars on chip, a comparative study based on worst-case losses. - Sébastien Le Beux; Hui Li 034; Gabriela Nicolescu; Jelena Trajkovic; Ian O'Connor (Concurr. Comput. Pract. Exp., 2014)

Modeling and simulation of networked low-power embedded systems: a taxonomy. - Wan Du; Fabien Mieyeville; David Navarro; Ian O'Connor; Laurent Carrel (EURASIP J. Wirel. Commun. Netw., 2014)

Energy-efficient optical crossbars on chip with multi-layer deposited silicon. - Hui Li 034; Sébastien Le Beux; Gabriela Nicolescu; Ian O'Connor (ASP-DAC, 2015)

Complementary communication path for energy efficient on-chip optical interconnects. - Hui Li 034; Sébastien Le Beux; Yvain Thonnart; Ian O'Connor (DAC, 2015)

LVS check for photonic integrated circuits: curvilinear feature extraction and validation. - Ruping Cao; Julien Billoudet; John Ferguson; Lionel Couder; John Cayo; Alexandre Arriordaz; Ian O'Connor (DATE, 2015)

Thermal aware design method for VCSEL-based on-chip optical interconnect. - Hui Li 034; Alain Fourmigue; Sébastien Le Beux; Xavier Letartre; Ian O'Connor; Gabriela Nicolescu (DATE, 2015)

Fast optical simulation from a reduced set of impulse responses using SystemC-AMS. - Fabien Teysseyre; David Navarro; Ian O'Connor; Francesco Cascio; Fabio Cenni; Olivier Guillaume (DATE, 2015)

Channel Allocation Protocol for Reconfigurable Optical Network-on-Chip. - Jiating Luo; Cédric Killian; Sébastien Le Beux; Daniel Chillet; Hui Li 034; Ian O'Connor; Olivier Sentieys (SiPhotonics@HiPEAC, 2015)

Multilevel Modeling Methodology for Reconfigurable Computing Systems Based on Silicon Photonics. - Zhen Li 046; Sébastien Le Beux; Christelle Monat; Xavier Letartre; Ian O'Connor (ISVLSI, 2015)

Communication Aware Design Method for Optical Network-on-Chip. - Johanna Sepúlveda; Sébastien Le Beux; Jiating Luo; Cédric Killian; Daniel Chillet; Hui Li 034; Ian O'Connor; Olivier Sentieys (MCSoC, 2015)

Full-adder circuit design based on all-spin logic device. - Qi An; Li Su; Jacques-Olivier Klein; Sébastien Le Beux; Ian O'Connor; Weisheng Zhao (NANOARCH, 2015)

Multi-Level Mapping of Nanocomputer Architectures Based on Hardware Reuse. - Nataliya Yakymets; Ian O'Connor; Kotb Jabeur; Sébastien Le Beux (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

An efficient and simple compact modeling approach for 3-D interconnects with IC's stack global electrical context consideration. - Jean-Etienne Lorival; Françis Calmon; Fengyuan Sun; Felipe Frantz; Carole Plossu; Martine Le Berre; Ian O'Connor; Olivier Valorge; Jean Charbonnier; David Henry; Christian Gontrand (Microelectron. J., 2015)

Foreword. - Jaan Raik; Ian O'Connor; Thomas Hollstein; Krishnendu Chakrabarty (VLSI-SoC, 2016)

Energy and Performance Trade-off in Nanophotonic Interconnects using Coding Techniques. - Cédric Killian; Daniel Chillet; Sébastien Le Beux; Van-Dung Pham; Olivier Sentieys; Ian O'Connor (DAC, 2017)

Performance and energy aware wavelength allocation on ring-based WDM 3D optical NoC. - Jiating Luo; A. Elantably; Van-Dung Pham; Cédric Killian; Daniel Chillet; Sébastien Le Beux; Olivier Sentieys; Ian O'Connor (DATE, 2017)

Hybrid Topologies for Reconfigurable Matrices Based on Nano-Grain Cells. - Kevin Cheng; Sébastien Le Beux; Ian O'Connor (ICRC, 2017)

An Energy-Efficient Reconfigurable Nanophotonic Computing Architecture Design: Optical Lookup Table. - Zhen Li 046; Christelle Monat; Sébastien Le Beux; Xavier Letartre; Ian O'Connor (ICRC, 2017)

Arithmetic Logic Unit based on all-spin logic devices. - Qi An; Sébastien Le Beux; Ian O'Connor; Jacques-Olivier Klein; Weisheng Zhao (NEWCAS, 2017)

Energy-Efficiency Comparison of Multi-Layer Deposited Nanophotonic Crossbar Interconnects. - Hui Li 034; Sébastien Le Beux; Martha Johanna Sepúlveda; Ian O'Connor (ACM J. Emerg. Technol. Comput. Syst., 2017)

Large scale, high density integration of all spin logic. - Qi An; Sébastien Le Beux; Ian O'Connor; Jacques-Olivier Klein (DATE, 2018)

Computing with ferroelectric FETs: Devices, models, systems, and applications. - Ahmedullah Aziz; Evelyn T. Breyer; An Chen; Xiaoming Chen 003; Suman Datta; Sumeet Kumar Gupta; Michael Hoffmann 008; Xiaobo Sharon Hu; Adrian M. Ionescu; Matthew Jerry; Thomas Mikolajick; Halid Mulaosmanovic; et al. (DATE, 2018)

Run-Time management of energy-performance trade-off in Optical Network-on-Chip. - Jiating Luo; Van-Dung Pham; Cédric Killian; Daniel Chillet; Ian O'Connor; Olivier Sentieys; Sébastien Le Beux (DCIS, 2018)

Systematic Design Method of Passive Ladder Filters using a Generalised Variable. - Arthur Perodou; Anton Korniienko; Gérard Scorletti; Ian O'Connor (DCIS, 2018)

CMOS VCSEL driver dedicated for sub-nanosecond laser pulses generation in SPAD-based time-of-flight rangefinder. - Samuel Rigault; Nicolas Moeneclaey; Lioua Labrak; Ian O'Connor (DCIS, 2018)

Prospects for energy-efficient edge computing with integrated HfO2-based ferroelectric devices. - Ian O'Connor; Mayeul Cantan; Cédric Marchand 002; Bertrand Vilquin; Stefan Slesazeck; Evelyn T. Breyer; Halid Mulaosmanovic; Thomas Mikolajick; Bastien Giraud; Jean-Philippe Noel; Adrian M. Ionescu; Igor Stolichnov (VLSI-SoC, 2018)

Offline Optimization of Wavelength Allocation and Laser Power in Nanophotonic Interconnects. - Jiating Luo; Cédric Killian; Sébastien Le Beux; Daniel Chillet; Olivier Sentieys; Ian O'Connor (ACM J. Emerg. Technol. Comput. Syst., 2018)

Towards Maximum Energy Efficiency in Nanophotonic Interconnects with Thermal-Aware On-Chip Laser Tuning. - Hui Li 034; Alain Fourmigue; Sébastien Le Beux; Ian O'Connor; Gabriela Nicolescu (IEEE Trans. Emerg. Top. Comput., 2018)

Guest Editorial: Emerging Technologies and Architectures for Manycore Computing Part 1: Hardware Techniques. - Sébastien Le Beux; Paul V. Gratz; Ian O'Connor (IEEE Trans. Multi Scale Comput. Syst., 2018)

Rebooting Computing: The Challenges for Test and Reliability. - Alberto Bosio; Ian O'Connor; Gennaro Severino Rodrigues; Fernanda Lima Kastensmidt; Elena I. Vatajelu; Giorgio Di Natale; Lorena Anghel; Surya Nagarajan; Moritz Fieback; Said Hamdioui (DFT, 2019)

A Low-Voltage Sub-ns Pulse Integrated CMOS Laser Diode Driver for SPAD-based Time-of-Flight Rangefinding in Mobile Applications. - Samuel Rigault; Nicolas Moeneclaey; Lioua Labrak; Ian O'Connor (SoCC, 2019)

Fast extraction of predictive models for integrated circuits using n-performance Pareto fronts. - Adil Brik; Lioua Labrak; Laurent Carrel; Ian O'Connor; Ramy Iskander (VLSI-SoC, 2019)

Guest Editors' Introduction: Emerging Networks-on-Chip Designs, Technologies, and Applications. - Edoardo Fusella; Mahdi Nikdast; Ian O'Connor; José Flich; Sudeep Pasricha (ACM J. Emerg. Technol. Comput. Syst., 2019)

A comprehensive compact model for the design of all-spin-logic based circuits. - Qi An; Sébastien Le Beux; Ian O'Connor; Jacques-Olivier Klein (Microelectron. J., 2019)

Thermal-Aware Design Method for Laser Group Control in Nanophotonic Interconnects. - Yuqi Wang; Amira Aouina; Hui Li 034; Ian O'Connor; Gabriela Nicolescu; Sébastien Le Beux (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Emerging Neural Workloads and Their Impact on Hardware. - David Brooks 001; Martin M. Frank; Tayfun Gokmen; Udit Gupta; Xiaobo Sharon Hu; Shubham Jain; Ann Franchesca Laguna; Michael T. Niemier; Ian O'Connor; Anand Raghunathan; Ashish Ranjan 001; Dayane Reis; et al. (DATE, 2020)

On the Automatic Exploration of Weight Sharing for Deep Neural Network Compression. - Etienne Dupuis; David Novo; Ian O'Connor; Alberto Bosio (DATE, 2020)

Sensitivity Analysis and Compression Opportunities in DNNs Using Weight Sharing. - Etienne Dupuis; David Novo; Ian O'Connor; Alberto Bosio (DDECS, 2020)

Exploiting Approximate Computing for implementing Low Cost Fault Tolerance Mechanisms. - Alberto Bosio; Ian O'Connor; Gennaro Severino Rodrigues; Fernanda Lima Lima; Said Hamdioui (DTIS, 2020)

Fast hierarchical system synthesis based on predictive models. - Adil Brik; Lioua Labrak; Ian O'Connor; Daniel Saias (NEWCAS, 2020)

3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model. - Arnaud Poittevin; Chhandak Mukherjee; Ian O'Connor; Cristell Maneux; Guilhem Larrieu; Marina Deng; Sébastien Le Beux; François Marc; Aurélie Lecestre; Cédric Marchand 002; Abhishek Kumar (VLSI-SoC (Selected Papers), 2020)

3D logic cells design and results based on Vertical NWFET technology including tied compact model. - C. Mukherjee 001; Marina Deng; François Marc; Cristell Maneux; Arnaud Poittevin; Ian O'Connor; Sébastien Le Beux; Abhishek Kumar; Aurélie Lecestre; Guilhem Larrieu (CoRR, 2020)

Emerging Technologies: Challenges and Opportunities for Logic Synthesis. - Alberto Bosio; Mayeul Cantan; Cédric Marchand 002; Ian O'Connor; Petr Fiser; Arnaud Poittevin; Marcello Traiola (DDECS, 2021)

AdequateDL: Approximating Deep Learning Accelerators. - Olivier Sentieys; Silviu-Ioan Filip; David Briand; David Novo; Etienne Dupuis; Ian O'Connor; Alberto Bosio (DDECS, 2021)

FeFET based Logic-in-Memory: an overview. - Cédric Marchand 002; Ian O'Connor; Mayeul Cantan; Evelyn T. Breyer; Stefan Slesazeck; Thomas Mikolajick (DTIS, 2021)

Emerging Computing Devices: Challenges and Opportunities for Test and Reliability*. - Alberto Bosio; Ian O'Connor; Marcello Traiola; Jorge Echavarria; Jürgen Teich; Muhammad Abdullah Hanif; Muhammad Shafique 001; Said Hamdioui; Bastien Deveautour; Patrick Girard 001; Arnaud Virazel; Koen Bertels (ETS, 2021)

Recent Advances in Photonic Physical Unclonable Functions. - Fabio Pavanello; Ian O'Connor; Ulrich Rührmair; Amy C. Foster; Dimitris Syvridis (ETS, 2021)

Design Space Exploration of Approximation-Based Quadruple Modular Redundancy Circuits. - Marcello Traiola; Jorge Echavarria; Alberto Bosio; Jürgen Teich; Ian O'Connor (ICCAD, 2021)

Fast Exploration of Weight Sharing Opportunities for CNN Compression. - Etienne Dupuis; David Novo; Ian O'Connor; Alberto Bosio (CoRR, 2021)

Holding Conferences Online in Pandemic Times: The DATE Experience. - Franco Fummi; Ian O'Connor (IEEE Des. Test, 2021)

Frequency Design of Lossless Passive Electronic Filters: A State-Space Formulation of the Direct Synthesis Approach. - Arthur Perodou; Anton Korniienko; Gérard Scorletti; Mykhailo Zarudniev; Jean-Baptiste David; Ian O'Connor (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Investigating data representation for efficient and reliable Convolutional Neural Networks. - Annachiara Ruospo; Ernesto Sánchez 001; Marcello Traiola; Ian O'Connor; Alberto Bosio (Microprocess. Microsystems, 2021)

Input-Aware Approximate Computing. - Ali Piri; Sepide Saeedi; Mario Barbareschi; Bastien Deveautour; Stefano Di Carlo; Ian O'Connor; Alessandro Savino; Marcello Traiola; Alberto Bosio (AQTR, 2022)

A Heuristic Exploration of Retraining-free Weight-Sharing for CNN Compression. - Etienne Dupuis; David Novo; Ian O'Connor; Alberto Bosio (ASP-DAC, 2022)

A Design Space Exploration Framework for Memristor-Based Crossbar Architecture. - Mario Barbareschi; Alberto Bosio; Ian O'Connor; Petr Fiser; Marcello Traiola (DDECS, 2022)

Dependability of Alternative Computing Paradigms for Machine Learning: hype or hope? - Cristiana Bolchini; Alberto Bosio; Luca Cassano; Bastien Deveautour; Giorgio Di Natale; Antonio Miele; Ian O'Connor; Elena-Ioana Vatajelu (DDECS, 2022)

Exploiting Approximate Computing for Efficient and Reliable Convolutional Neural Networks. - Alberto Bosio; Bastien Deveautour; Ian O'Connor (ISVLSI, 2022)

Hardware Emulation of FeFET On FPGA. - Paul-Antoine Matrangolo; Cédric Marchand 002; David Navarro; Ian O'Connor (ISVLSI, 2022)

Energy efficient on-chip optical broadcast with partial-absorption photodiodes. - Raphael Cardoso; Lubna Arif; Clément Zrounba; Fabio Pavanello; Ian O'Connor; Laurent Vivien; Léopold Virot; Sébastien Le Beux (NEWCAS, 2022)

A Logic Cell Design and routing Methodology Specific to VNWFET. - Arnaud Poittevin; Ian O'Connor; Cédric Marchand 002; Alberto Bosio; Cristell Maneux; Chhandak Mukherjee; Guilhem Larrieu; Abhishek Kumar (NEWCAS, 2022)

Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors. - Lucas Réveil; Chhandak Mukherjee; Cristell Maneux; Marina Deng; François Marc; Abhishek Kumar; Aurélie Lecestre; Guilhem Larrieu; Arnaud Poittevin; Ian O'Connor; Oskar Baumgartner; David Pirker (VLSI-SoC, 2022)

Approximations in Deep Learning. - Etienne Dupuis; Silviu-Ioan Filip; Olivier Sentieys; David Novo; Ian O'Connor; Alberto Bosio (CoRR, 2022)

Towards a Robust Multiply-Accumulate Cell in Photonics using Phase-Change Materials. - Raphael Cardoso; Clément Zrounba; Mohab Abdalla; Paul Jiménez; Mauricio Gomes de Queiroz; Benoît Charbonnier; Fabio Pavanello; Ian O'Connor; Sébastien Le Beux (DATE, 2023)

Cross Layer Design for the Predictive Assessment of Technology-Enabled Architectures. - Michael T. Niemier; Xiaobo Sharon Hu; Liu Liu; Mohammad Mehdi Sharifi; Ian O'Connor; David Atienza; Giovanni Ansaloni; Can Li; Asif Khan; Daniel C. Ralph (DATE, 2023)

Lightspeed Binary Neural Networks using Optical Phase-Change Materials. - Taha Shahroodi; Raphael Cardoso; Mahdi Zahedi; Stephan Wong; Alberto Bosio; Ian O'Connor; Said Hamdioui (DATE, 2023)

Resilience-Performance Tradeoff Analysis of a Deep Neural Network Accelerator. - Salvatore Pappalardo; Annachiara Ruospo; Ian O'Connor; Bastien Deveautour; Ernesto Sánchez 001; Alberto Bosio (DDECS, 2023)

Investigating the effect of approximate multipliers on the resilience of a systolic array DNN accelerator. - Salvatore Pappalardo; Ali Piri; Annachiara Ruospo; Ian O'Connor; Bastien Deveautour; Ernesto Sánchez 001; Alberto Bosio (DFT, 2023)

Input-aware accuracy characterization for approximate circuits. - Ali Piri; Salvatore Pappalardo; Salvatore Barone; Mario Barbareschi; Bastien Deveautour; Marcello Traiola; Ian O'Connor; Alberto Bosio (DSN-W, 2023)

Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design. - Yifan Wang; Chhandak Mukherjee; Houssem Rezgui; Marina Deng; Cristell Maneux; Sara Mannaa; Ian O'Connor; Jonas Müller; Sylvain Pelloquin; Guilhem Larrieu (ESSDERC, 2023)

EUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS. - Fabio Pavanello; Cédric Marchand 002; Ian O'Connor; Régis Orobtchouk; Fabien Mandorlo; Xavier Letartre; Sébastien Cueff; Elena-Ioana Vatajelu; Giorgio Di Natale; Benoit Cluzel; Aurelien Coillet; Benoît Charbonnier; et al. (ETS, 2023)

Invited Paper: Algorithm/Hardware Co-Design for Few-Shot Learning at the Edge. - Ann Franchesca Laguna; Mohammad Mehdi Sharifi; Dayane Reis; Liu Liu; Andrew Hennessee; Clayton O'Dell; Ian O'Connor; Michael T. Niemier; X. Sharon Hu (ICCAD, 2023)

Energy-efficient Computation-In-Memory Architecture using Emerging Technologies. - Rajendra Bishnoi; Sumit Diware; Anteneh Gebregiorgis; Simon Thomann; Sara Mannaa; Bastien Deveautour; Cédric Marchand 002; Alberto Bosio; Damien Deleruyelle; Ian O'Connor; Hussam Amrouch; Said Hamdioui (ICM, 2023)

Photonic Convolution Engine Based on Phase-Change Materials and Stochastic Computing. - Raphael Cardoso; Clément Zrounba; Mohab Abdalla; Paul Jiménez; Mauricio Gomes de Queiroz; Benoît Charbonnier; Fabio Pavanello; Ian O'Connor; Sébastien Le Beux (ISVLSI, 2023)

A Fault Injection Framework for AI Hardware Accelerators. - Salvatore Pappalardo; Annachiara Ruospo; Ian O'Connor; Bastien Deveautour; Ernesto Sánchez 001; Alberto Bosio (LATS, 2023)

FeFET based Logic-in-Memory design methodologies, tools and open challenges. - Cédric Marchand 002; Alban Nicolas; Paul-Antoine Matrangolo; David Navarro; Alberto Bosio; Ian O'Connor (VLSI-SoC, 2023)

NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS. - Fabio Pavanello; Cédric Marchand 002; Ian O'Connor; Régis Orobtchouk; Fabien Mandorlo; Xavier Letartre; Sébastien Cueff; Elena-Ioana Vatajelu; Giorgio Di Natale; Benoit Cluzel; Aurelien Coillet; Benoît Charbonnier; et al. (CoRR, 2023)

Postpandemic Conferences: The DATE 2023 Experience. - Ian O'Connor; Robert Wille; Andy D. Pimentel; Valeria Bertacco (IEEE Des. Test, 2023)

Signed Convolution in Photonics with Phase-Change Materials using Mixed-Polarity Bitstreams. - Raphael Cardoso; Clément Zrounba; Mohab Abdalla; Paul Jiménez; Mauricio Gomes de Queiroz; Benoît Charbonnier; Fabio Pavanello; Ian O'Connor; Sébastien Le Beux (ASPDAC, 2024)

Smoothing Disruption Across the Stack: Tales of Memory, Heterogeneity, & Compilers. - Michael T. Niemier; Zephan M. Enciso; M. Sharifi; Xiaobo Sharon Hu; Ian O'Connor; A. Graening; R. Sharma; P. Gupta; Jerónimo Castrillón; João Paulo C. de Lima; Asif Ali Khan; Hamid Farzaneh; et al. (DATE, 2024)

FVLLMONTI: The 3D Neural Network Compute Cube $(N^{2}C^{2})$ Concept for Efficient Transformer Architectures Towards Speech-to-Speech Translation. - Ian O'Connor; Sara Mannaa; Alberto Bosio; Bastien Deveautour; Damien Deleruyelle; Tetiana Obukhova; Cédric Marchand 002; Jens Trommer; Çigdem Çakirlar; Bruno Neckel Wesling; Thomas Mikolajick; Oskar Baumgartner; et al. (DATE, 2024)

High-Performance Data Mapping for BNNs on PCM-Based Integrated Photonics. - Taha Shahroodi; Raphael Cardoso; Stephan Wong; Alberto Bosio; Ian O'Connor; Said Hamdioui (DATE, 2024)

3D VNWFET-Based Standard Cell Library Design Flow: from Circuit and Physical Design to Logic Synthesis. - Sara Mannaa; Cédric Marchand 002; Damien Deleruyelle; Bastien Deveautour; Alberto Bosio; Christoph Lenz; Oskar Baumgartner; Ian O'Connor (VLSI-SoC, 2024)

A Novel Design Technique for Enhanced Security and New Applications of Ferroelectric-Based Non-Volatile SRAM. - Lucas Rhetat; Jean-Philippe Noel; Bastien Giraud; Laurent Grenouillet; Julie Laguerre; Cédric Marchand 002; Ian O'Connor (VLSI-SoC, 2024)

The Impact of Feature Representation on the Accuracy of Photonic Neural Networks. - Mauricio Gomes de Queiroz; Paul Jiménez; Raphael Cardoso; Mateus Vidaletti Costa; Mohab Abdalla; Ian O'Connor; Alberto Bosio; Fabio Pavanello (CoRR, 2024)

Improving Chip Design Enablement for Universities in Europe - A Position Paper. - Lukas Krupp; Ian O'Connor; Luca Benini; Christoph Studer; Joachim Rodrigues; Norbert Wehn (DATE, 2025)

Bi-Linearity of Back Gated Schottky Barrier Transistors on an Industrial 22nm FDSOI Platform for Efficient In-Hardware Matrix-Vector Multiplication and Addition. - Juan P. Martinez; Niladri Bhattacharjee; Yuxuan He; Giulio Galderisi; Ian O'Connor; Thomas Mikolajick; Jens Trommer (NewCAS, 2025)