A 9-kbit associative memory for high-speed parallel processing applications. - Simon R. Jones; Ian P. Jalowiecki; Stephen J. Hedge; R. Mike Lea (IEEE J. Solid State Circuits, 1988)

The WASP 2 Wafer Scale Integration Demonstrator. - Ian P. Jalowiecki; Stephen J. Hedge (VLSI, 1991)

Associative massively parallel computers. - R. Mike Lea; Ian P. Jalowiecki (Proc. IEEE, 1991)

The implementation of a MCM associative string processor. - Claus M. Habiger; Ian P. Jalowiecki (VLSI, 1993)

An Implementation Of A Set Mode For Prolog On A Parallell Associative Processor. - Darren Patrick Rodohan; Ray J. Glover; Ian P. Jalowiecki (PDP, 1994)

MCM Quality and Cost Analysis Using Economics Models. - Chryssa Dislis; A. F. Al-Ani; Ian P. Jalowiecki (ITC, 1995)

Economics Modelling and Optimisation of MCM Test Strategies. - Chryssa Dislis; Ian P. Jalowiecki (ED&TC, 1996)

The Prediction of Circuit Performance Variations for Deep Submicron CMOS Processes. - Thomas Gneiting; Ian P. Jalowiecki (DFT, 1996)

A programmable processor with 4096 processing units for media applications. - Argy Krikelis; Ian P. Jalowiecki; David L. Bean; Ryan Bishop; M. Facey; D. Boughton; S. Murphy; M. Whitaker (ICASSP, 2001)