6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET. - Jay Im; Dave Freitas; Arianne Roldan; Ronan Casey; Stanley Chen; Adam Chou; Tim Cronin; Kevin Geary; Scott McLeod; Lei Zhou; Ian Zhuang; Jaeduk Han; et al. (ISSCC, 2017)

A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET. - Jay Im; Dave Freitas; Arianne Roldan; Ronan Casey; Stanley Chen; Adam Chou; Tim Cronin; Kevin Geary; Scott McLeod; Lei Zhou; Ian Zhuang; Jaeduk Han; et al. (IEEE J. Solid State Circuits, 2017)

A 4-to-16GHz inverter-based injection-locked quadrature clock generator with phase interpolators for multi-standard I/Os in 7nm FinFET. - Stanley Chen; Lei Zhou; Ian Zhuang; Jay Im; Didem Turker Melek; Jinyung Namkoong; Mayank Raj; Jaewook Shin; Yohan Frans; Ken Chang (ISSCC, 2018)

A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET. - Jay Im; Stanley Chen; Dave Freitas; Adam Chou; Lei Zhou; Ian Zhuang; Tim Cronin; David Mahashin; Winson Lin; Kok Lim Chan; Hongyuan Zhao; Kee Hian Tan; et al. (VLSI Circuits, 2018)