Adaptive History-Based Memory Schedulers. - Ibrahim Hur; Calvin Lin (MICRO, 2004)

Memory Prefetching Using Adaptive Stream Detection. - Ibrahim Hur; Calvin Lin (MICRO, 2006)

Adaptive History-Based Memory Schedulers for Modern Processors. - Ibrahim Hur; Calvin Lin (IEEE Micro, 2006)

Memory scheduling for modern microprocessors. - Ibrahim Hur; Calvin Lin (ACM Trans. Comput. Syst., 2007)

A comprehensive approach to DRAM power management. - Ibrahim Hur; Calvin Lin (HPCA, 2008)

Feedback mechanisms for improving probabilistic memory prefetching. - Ibrahim Hur; Calvin Lin (HPCA, 2009)

Discovering and understanding performance bottlenecks in transactional applications. - Ferad Zyulkyarov; Srdjan Stipic; Tim Harris 001; Osman S. Unsal; Adrián Cristal; Ibrahim Hur; Mateo Valero (PACT, 2010)

The Velox Transactional Memory Stack. - Yehuda Afek; Ulrich Drepper; Pascal Felber; Christof Fetzer; Vincent Gramoli; Michael Hohmuth; Etienne Rivière; Per Stenström; Osman S. Unsal; Walther Maldonado; Derin Harmanci; Patrick Marlier; et al. (IEEE Micro, 2010)

Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory. - Adrià Armejach; Azam Seyedi; J. Rubén Titos Gil; Ibrahim Hur; Adrián Cristal; Osman S. Unsal; Mateo Valero (PACT, 2011)

STM2: A Parallel STM for High Performance Simultaneous Multithreading Systems. - Gokcen Kestor; Roberto Gioiosa; Tim Harris 001; Osman S. Unsal; Adrián Cristal; Ibrahim Hur; Mateo Valero (PACT, 2011)

SymptomTM: Symptom-Based Error Detection and Recovery Using Hardware Transactional Memory. - Gulay Yalcin; Osman S. Unsal; Adrián Cristal; Ibrahim Hur; Mateo Valero (PACT, 2011)

From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype. - Nehir Sönmez; Oriol Arcas; Gokhan Sayilar; Osman S. Unsal; Adrián Cristal; Ibrahim Hur; Satnam Singh; Mateo Valero (ARC, 2011)

TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System. - Nehir Sönmez; Oriol Arcas; Otto Pflucker; Osman S. Unsal; Adrián Cristal; Ibrahim Hur; Satnam Singh; Mateo Valero (FCCM, 2011)

Circuit design of a dual-versioning L1 data cache for optimistic concurrency. - Azam Seyedi; Adrià Armejach; Adrián Cristal; Osman S. Unsal; Ibrahim Hur; Mateo Valero (ACM Great Lakes Symposium on VLSI, 2011)

RMS-TM: a comprehensive benchmark suite for transactional memory systems. - Gokcen Kestor; Vasileios Karakostas; Osman S. Unsal; Adrián Cristal; Ibrahim Hur; Mateo Valero (ICPE, 2011)

RMS-TM: a comprehensive benchmark suite for transactional memory systems (abstracts only). - Gokcen Kestor; Vasileios Karakostas; Osman S. Unsal; Adrián Cristal; Ibrahim Hur; Mateo Valero (SIGMETRICS Perform. Evaluation Rev., 2011)

Power-aware multi-core simulation for early design stage hardware/software co-optimization. - Wim Heirman; Souradip Sarkar; Trevor E. Carlson; Ibrahim Hur; Lieven Eeckhout (PACT, 2012)

Profiling and Optimizing Transactional Memory Applications. - Ferad Zyulkyarov; Srdjan Stipic; Tim Harris 001; Osman S. Unsal; Adrián Cristal; Ibrahim Hur; Mateo Valero (Int. J. Parallel Program., 2012)

Circuit design of a dual-versioning L1 data cache. - Azam Seyedi; Adrià Armejach; Adrián Cristal; Osman S. Unsal; Ibrahim Hur; Mateo Valero (Integr., 2012)

Resource-bounded multicore emulation using Beefarm. - Oriol Arcas; Nehir Sönmez; Gokhan Sayilar; Satnam Singh; Osman S. Unsal; Adrián Cristal; Ibrahim Hur; Mateo Valero (Microprocess. Microsystems, 2012)

Hardware transactional memory with software-defined conflicts. - J. Rubén Titos Gil; Manuel E. Acacio; José M. García 001; Tim Harris 001; Adrián Cristal; Osman S. Unsal; Ibrahim Hur; Mateo Valero (ACM Trans. Archit. Code Optim., 2012)

Undersubscribed threading on clustered cache architectures. - Wim Heirman; Trevor E. Carlson; Kenzo Van Craeynest; Ibrahim Hur; Aamer Jaleel; Lieven Eeckhout (HPCA, 2014)

Automatic SMT threading for OpenMP applications on the Intel Xeon Phi co-processor. - Wim Heirman; Trevor E. Carlson; Kenzo Van Craeynest; Ibrahim Hur; Aamer Jaleel; Lieven Eeckhout (ROSS@ICS, 2014)

An Evaluation of High-Level Mechanistic Core Models. - Trevor E. Carlson; Wim Heirman; Stijn Eyerman; Ibrahim Hur; Lieven Eeckhout (ACM Trans. Archit. Code Optim., 2014)

Initial results on computational performance of Intel many integrated core, sandy bridge, and graphical processing unit architectures: implementation of a 1D c++/OpenMP electrostatic particle-in-cell code. - A. Vapirev; Jan Deca; Giovanni Lapenta; Stefano Markidis; Ibrahim Hur; Jean-Luc Cambier (Concurr. Comput. Pract. Exp., 2015)

Exploring optimizations on shared-memory platforms for parallel triangle counting algorithms. - Ancy Sarah Tom; Narayanan Sundaram; Nesreen K. Ahmed; Shaden Smith; Stijn Eyerman; Midhunchandra Kodiyath; Ibrahim Hur; Fabrizio Petrini; George Karypis (HPEC, 2017)

Near-side prefetch throttling: adaptive prefetching for high-performance many-core processors. - Wim Heirman; Kristof Du Bois; Yves Vandriessche; Stijn Eyerman; Ibrahim Hur (PACT, 2018)

Extending the Performance Analysis Tool Box: Multi-stage CPI Stacks and FLOPS Stacks. - Stijn Eyerman; Wim Heirman; Kristof Du Bois; Ibrahim Hur (ISPASS, 2018)

Many-core graph workload analysis. - Stijn Eyerman; Wim Heirman; Kristof Du Bois; Joshua B. Fryman; Ibrahim Hur (SC, 2018)

Multi-Stage CPI Stacks. - Stijn Eyerman; Wim Heirman; Kristof Du Bois; Ibrahim Hur (IEEE Comput. Archit. Lett., 2018)

Efficient Sparse Matrix-Vector Multiplication on Intel PIUMA Architecture. - Sriram Aananthakrishnan; Robert Pawlowski; Joshua B. Fryman; Ibrahim Hur (HPEC, 2020)

Projecting Performance for PIUMA using Down-Scaled Simulation. - Stijn Eyerman; Wim Heirman; Yigit Demir; Kristof Du Bois; Ibrahim Hur (HPEC, 2020)

Hash Table Scalability on Intel PIUMA. - Balasubramanian Seshasayee; Joshua B. Fryman; Ibrahim Hur (HPEC, 2020)

Breaking In-Order Branch Miss Recovery. - Stijn Eyerman; Wim Heirman; Sam Van den Steen; Ibrahim Hur (IEEE Comput. Archit. Lett., 2020)

PIUMA: Programmable Integrated Unified Memory Architecture. - Sriram Aananthakrishnan; Nesreen K. Ahmed; Vincent Cavé; Marcelo Cintra; Yigit Demir; Kristof Du Bois; Stijn Eyerman; Joshua B. Fryman; Ivan Ganev; Wim Heirman; Hans-Christian Hoppe; Jason Howard; et al. (CoRR, 2020)

Enabling Branch-Mispredict Level Parallelism by Selectively Flushing Instructions. - Stijn Eyerman; Wim Heirman; Sam Van den Steen; Ibrahim Hur (MICRO, 2021)

Modeling DRAM Timing in Parallel Simulators With Immediate-Response Memory Model. - Stijn Eyerman; Wim Heirman; Ibrahim Hur (IEEE Comput. Archit. Lett., 2021)

RIO: ROB-Centric In-Order Modeling of Out-of-Order Processors. - Wim Heirman; Stijn Eyerman; Kristof Du Bois; Ibrahim Hur (IEEE Comput. Archit. Lett., 2021)

Automatic Sublining for Efficient Sparse Memory Accesses. - Wim Heirman; Stijn Eyerman; Kristof Du Bois; Ibrahim Hur (ACM Trans. Archit. Code Optim., 2021)

Towards a GraphBLAS Implementation for Go. - Pascal Costanza; Ibrahim Hur; Timothy G. Mattson (IPDPS Workshops, 2022)

DRAM Bandwidth and Latency Stacks: Visualizing DRAM Bottlenecks. - Stijn Eyerman; Wim Heirman; Ibrahim Hur (ISPASS, 2022)

Efficient Asynchronous RPC Calls for Microservices: DeathStarBench Study. - Stijn Eyerman; Ibrahim Hur (CoRR, 2022)

Simulating Wrong-Path Instructions in Decoupled Functional-First Simulation. - Stijn Eyerman; Sam Van den Steen; Wim Heirman; Ibrahim Hur (ISPASS, 2023)

The Intel Programmable and Integrated Unified Memory Architecture Graph Analytics Processor. - Sriram Aananthakrishnan; Shamsul Abedin; Vincent Cavé; Fabio Checconi; Kristof Du Bois; Stijn Eyerman; Joshua B. Fryman; Wim Heirman; Jason Howard; Ibrahim Hur; Samkit Jain; Marek M. Landowski; et al. (IEEE Micro, 2023)

HotTiles: Accelerating SpMM with Heterogeneous Accelerator Architectures. - Gerasimos Gerogiannis; Sriram Aananthakrishnan; Josep Torrellas; Ibrahim Hur (HPCA, 2024)

Accurate and Scalable Many-Node Simulation. - Stijn Eyerman; Wim Heirman; Kristof Du Bois; Ibrahim Hur (CoRR, 2024)