Switch-Level Logic Simulation of Digital Bipolar Circuits. - Ibrahim N. Hajj; Daniel G. Saab (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

Delay Modeling and Time of Bipolar Digital Circuits. - Daniel G. Saab; Andrew T. Yang; Ibrahim N. Hajj (DAC, 1988)

iPRIDE: a parallel integrated circuit simulator using direct method. - Mi-Chang Chang; Ibrahim N. Hajj (ICCAD, 1988)

CREST-a current estimator for CMOS circuits. - Farid N. Najm; Richard Burch; Ping Yang 001; Ibrahim N. Hajj (ICCAD, 1988)

A tabular macromodeling approach to fast timing simulation including parasitics. - David Overhauser; Ibrahim N. Hajj (ICCAD, 1988)

iEDISON: an interactive statistical design tool for MOS VLSI circuits. - Tat-Kwan Yu; Sung-Mo Kang; Ibrahim N. Hajj; Timothy N. Trick (ICCAD, 1988)

A custom cell generation system for double-metal CMOS technology. - P. Gee; Ibrahim N. Hajj; Sung-Mo Kang (ICCAD, 1989)

Computation of bus current variance for reliability estimation of VLSI circuits. - Farid N. Najm; Ibrahim N. Hajj; Ping Yang 001 (ICCAD, 1989)

Automatic mixed-mode timing simulation. - David Overhauser; Ibrahim N. Hajj; Yi-Fan Hsu (ICCAD, 1989)

Electromigration median time-to-failure based on a stochastic current waveform. - Farid N. Najm; Ibrahim N. Hajj; Ping Yang 001 (ICCD, 1989)

Parallel-concurrent fault simulation. - Daniel G. Saab; Ibrahim N. Hajj; Joseph T. Rahmeh (ICCD, 1989)

Switching network logic approach to sequential MOS circuit design. - Min-You Wu; Ibrahim N. Hajj (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

An Algebra for Switch-Level Simulation. - Ibrahim N. Hajj (ICCAD, 1990)

High speed VLSI logic simulation using bitwise operations and parallel processing. - Young-Hyun Jun; Ibrahim N. Hajj; Sang-Heon Lee; Song-Bai Park (ICCD, 1990)

A metal - metal matrix cell generator for multi-level metal MOS technology. - P. Gee; Min-You Wu; S. M. Kang; Ibrahim N. Hajj (Integr., 1990)

A multilevel parallel solver for block tridiagonal and banded linear systems. - Ibrahim N. Hajj; Stig Skelboe (Parallel Comput., 1990)

Probabilistic simulation for reliability analysis of CMOS VLSI circuits. - Farid N. Najm; Richard Burch; Ping Yang 001; Ibrahim N. Hajj (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

The complexity of fault detection in MOS VLSI circuits. - Farid N. Najm; Ibrahim N. Hajj (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

A Switch-Level Matrix Approach to Transistor-Level Fault Simulation. - Terry Lee; Ibrahim N. Hajj (ICCAD, 1991)

An extension of probabilistic simulation for reliability analysis of CMOS VLSI circuits. - Farid N. Najm; Ibrahim N. Hajj; Ping Yang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Maximum Current Estimation in CMOS Circuits. - Harish Kriplani; Farid N. Najm; Ibrahim N. Hajj (DAC, 1992)

ACCORD: Automatic Catching and CORrection of Logic Design Errors in Combinatorial Circuits. - Pi-Yu Chung; Ibrahim N. Hajj (ITC, 1992)

Simulation of physical faults in VLSI circuits. - Ibrahim N. Hajj; Terry Lee (VTS, 1992)

Diagnosis and Correction of Logic Design Errors in Digital Circuits. - Pi-Yu Chung; Yi-Min Wang; Ibrahim N. Hajj (DAC, 1993)

Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits. - Harish Kriplani; Farid N. Najm; Ping Yang 001; Ibrahim N. Hajj (DAC, 1993)

Improved Techniques for Probabilistic Simulation Including Signal Correlation Effects. - Georgios I. Stamoulis; Ibrahim N. Hajj (DAC, 1993)

A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area. - Weitong Chuang; Sachin S. Sapatnekar; Ibrahim N. Hajj (ICCAD, 1993)

Fast Mixed-Mode Simulation for Accurate MOS Bridging Fault Detection. - Weitong Chuang; Ibrahim N. Hajj (ISCAS, 1993)

Efficient Variable Ordering Heuristics for Shared ROBDD. - Pi-Yu Chung; Ibrahim N. Hajj; Janak H. Patel (ISCAS, 1993)

Switch-level timing simulation of bipolar ECL circuits. - Andrew T. Yang; Yu-Hsu Chang; Daniel G. Saab; Ibrahim N. Hajj (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Delay and area optimization for compact placement by gate resizing and relocation. - Weitong Chuang; Ibrahim N. Hajj (ICCAD, 1994)

Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits. - Harish Kriplani; Farid N. Najm; Ibrahim N. Hajj (ISCAS, 1994)

A probabilistic timing approach to hot-carrier effect estimation. - Ping-Chung Li; Georgios I. Stamoulis; Ibrahim N. Hajj (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Logic design error diagnosis and correction. - Pi-Yu Chung; Yi-Min Wang; Ibrahim N. Hajj (IEEE Trans. Very Large Scale Integr. Syst., 1994)

Power Estimation in Sequential Circuits. - Farid N. Najm; Shashank Goel; Ibrahim N. Hajj (DAC, 1995)

Timing and area optimization for standard-cell VLSI circuit design. - Weitong Chuang; Sachin S. Sapatnekar; Ibrahim N. Hajj (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution. - Harish Kriplani; Farid N. Najm; Ibrahim N. Hajj (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Circuit-level dictionaries of CMOS bridging faults. - Terry Lee; Weitong Chuang; Ibrahim N. Hajj; W. Kent Fuchs (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits. - Terry Lee; Ibrahim N. Hajj; Elizabeth M. Rudnick; Janak H. Patel (VTS, 1996)

Computer-aided redesign of VLSI circuits for hot-carrier reliability. - Ping-Chung Li; Ibrahim N. Hajj (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Analytical Estimation of Transition Activity From Word-Level Signal Statistics. - Sumant Ramprasad; Naresh R. Shanbhag; Ibrahim N. Hajj (DAC, 1997)

Monte-Carlo approach for power estimation in sequential circuits. - Vikram Saxena; Farid N. Najm; Ibrahim N. Hajj (ED&TC, 1997)

A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits. - Andreas G. Veneris; Ibrahim N. Hajj (Great Lakes Symposium on VLSI, 1997)

GOLDENGATE: a fast and accurate bridging fault simulator under a hybrid logic/IDDQ testing environment. - Tzuhao Chen; Ibrahim N. Hajj (ICCAD, 1997)

Achievable bounds on signal transition activity. - Sumant Ramprasad; Naresh R. Shanbhag; Ibrahim N. Hajj (ICCAD, 1997)

Analytical estimation of signal transition activity from word-level statistics. - Sumant Ramprasad; Naresh R. Shanbhag; Ibrahim N. Hajj (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Diagnosis and correction of multiple logic design errors in digital circuits. - Pi-Yu Chung; Ibrahim N. Hajj (IEEE Trans. Very Large Scale Integr. Syst., 1997)

Maximum Current Estimation in Programmable Logic Arrays. - Sudhakar Bobba; Ibrahim N. Hajj (Great Lakes Symposium on VLSI, 1998)

Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors. - Nikolaos Bellas; Ibrahim N. Hajj; George D. Stamoulis; Constantine D. Polychronopoulos (ISLPED, 1998)

Decorrelating (DECOR) transformations for low-power adaptive filters. - Sumant Ramprasad; Naresh R. Shanbhag; Ibrahim N. Hajj (ISLPED, 1998)

Estimation of maximum current envelope for power bus analysis and design. - Sudhakar Bobba; Ibrahim N. Hajj (ISPD, 1998)

Coding for Low-Power Address and Data Busses: A Source-Coding Framework and Applications. - Sumant Ramprasad; Naresh R. Shanbhag; Ibrahim N. Hajj (VLSI Design, 1998)

An Exact Analytical Time-Domain Model Of Distributed RC Interconnects for High Speed Nonlinear Circuit Applications. - Ninglong Lu; Ibrahim N. Hajj (Great Lakes Symposium on VLSI, 1999)

Energy and Performance Improvements in Microprocessor Design Using a Loop Cache. - Nikolaos Bellas; Ibrahim N. Hajj; Constantine D. Polychronopoulos; George D. Stamoulis (ICCD, 1999)

A hybrid approach to design error detection and correction [VLSI digital circuits]. - Andreas G. Veneris; Ibrahim N. Hajj (ICECS, 1999)

An analytical, transistor-level energy model for SRAM-based caches. - Nikolaos Bellas; Ibrahim N. Hajj; Constantine D. Polychronopoulos (ISCAS (6), 1999)

A reduced-order scheme for coupled lumped-distributed interconnect simulation. - Ninglong Lu; Ibrahim N. Hajj (ISCAS (6), 1999)

Low-power distributed arithmetic architectures using nonuniform memory partitioning. - Sumant Ramprasad; Naresh R. Shanbhag; Ibrahim N. Hajj (ISCAS (3), 1999)

Correcting multiple design errors in digital VLSI circuits. - Andreas G. Veneris; Ibrahim N. Hajj (ISCAS (1), 1999)

Using dynamic cache management techniques to reduce energy in a high-performance processor. - Nikolaos Bellas; Ibrahim N. Hajj; Constantine D. Polychronopoulos (ISLPED, 1999)

An optimization technique for dual-output domino logic. - Sumant Ramprasad; Ibrahim N. Hajj; Farid N. Najm (ISLPED, 1999)

Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures. - Sudhakar Bobba; Ibrahim N. Hajj; Naresh R. Shanbhag (VLSI Design, 1999)

Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits. - Andreas G. Veneris; Ibrahim N. Hajj; Srikanth Venkataraman; W. Kent Fuchs (VTS, 1999)

Design error diagnosis and correction via test vector simulation. - Andreas G. Veneris; Ibrahim N. Hajj (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

A coding framework for low-power address and data busses. - Sumant Ramprasad; Naresh R. Shanbhag; Ibrahim N. Hajj (IEEE Trans. Very Large Scale Integr. Syst., 1999)

Information-theoretic bounds on average signal transition activity [VLSI systems]. - Sumant Ramprasad; Naresh R. Shanbhag; Ibrahim N. Hajj (IEEE Trans. Very Large Scale Integr. Syst., 1999)

High-performance bidirectional repeaters. - Sudhakar Bobba; Ibrahim N. Hajj (ACM Great Lakes Symposium on VLSI, 2000)

Peak current estimation for digital filters. - Sudhakar Bobba; Ibrahim N. Hajj (ICASSP, 2000)

Simulation and Optimization of the Power Distribution Network in VLSI Circuits. - Geng Bai; Sudhakar Bobba; Ibrahim N. Hajj (ICCAD, 2000)

Current-Mode Threshold Logic Gates. - Sudhakar Bobba; Ibrahim N. Hajj (ICCD, 2000)

An analytical model for delay and crosstalk estimation in interconnects under general switching conditions. - Murat R. Becer; Ibrahim N. Hajj (ICECS, 2000)

A hierarchical based approach for coupling aware delay analysis of combinational logic blocks. - Ninglong Lu; Ibrahim N. Hajj (ICECS, 2000)

Instruction scheduling for low power on dynamically variable voltage processors. - Mohammad M. Mansour; Makram M. Mansour; Ibrahim N. Hajj; Naresh R. Shanbhag (ICECS, 2000)

Power Bus Maximum Voltage Drop in Digital VLSI Circuits. - Geng Bai; Sudhakar Bobba; Ibrahim N. Hajj (ISQED, 2000)

An Analytical Model for Delay and Crosstalk Estimation with Application to Decoupling. - Murat R. Becer; Ibrahim N. Hajj (ISQED, 2000)

Using dynamic cache management techniques to reduce energy in general purpose processors. - Nikolaos Bellas; Ibrahim N. Hajj; Constantine D. Polychronopoulos (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Architectural and compiler techniques for energy reduction in high-performance microprocessors. - Nikolaos Bellas; Ibrahim N. Hajj; Constantine D. Polychronopoulos; George I. Stamoulis (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits. - Geng Bai; Sudhakar Bobba; Ibrahim N. Hajj (DAC, 2001)

Maximum power supply noise estimation in VLSI circuits using multimodal genetic algorithms. - Geng Bai; Sudhakar Bobba; Ibrahim N. Hajj (ICECS, 2001)

Input vector generation for maximum intrinsic decoupling capacitance of VLSI circuits. - Sudhakar Bobba; Ibrahim N. Hajj (ISCAS (5), 2001)

Maximum voltage variation in the power distribution network of VLSI circuits with RLC models. - Sudhakar Bobba; Ibrahim N. Hajj (ISLPED, 2001)

RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits. - Geng Bai; Sudhakar Bobba; Ibrahim N. Hajj (ISQED, 2001)

A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance. - Murat R. Becer; David T. Blaauw; Supamas Sirichotiyakul; Chanhee Oh; Vladimir Zolotov; Jingyan Zuo; Rafi Levy; Ibrahim N. Hajj (ISQED, 2001)

A Fast Coupling Aware Delay Estimation Scheme Based on Simplified Circuit Model. - Ninglong Lu; Ibrahim N. Hajj (ISQED, 2001)

Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model . - Murat R. Becer; Vladimir Zolotov; David T. Blaauw; Rajendran Panda; Ibrahim N. Hajj (DATE, 2002)

Simultaneous Switching Noise and Resonance Analysis of On-Chip Power Distribution Network. - Geng Bai; Ibrahim N. Hajj (ISQED, 2002)

Pre-route Noise Estimation in Deep Submicron Integrated Circuits. - Murat R. Becer; Rajendran Panda; David T. Blaauw; Ibrahim N. Hajj (ISQED, 2002)

Estimation of state line statistics in sequential circuits. - Vikram Saxena; Farid N. Najm; Ibrahim N. Hajj (ACM Trans. Design Autom. Electr. Syst., 2002)

A technique for Improving dual-output domino logic. - Sumant Ramprasad; Ibrahim N. Hajj; Farid N. Najm (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Post-route gate sizing for crosstalk noise reduction. - Murat R. Becer; David T. Blaauw; Ilan Algor; Rajendran Panda; Chanhee Oh; Vladimir Zolotov; Ibrahim N. Hajj (DAC, 2003)

Early probabilistic noise estimation for capacitively coupled interconnects. - Murat R. Becer; David T. Blaauw; Rajendran Panda; Ibrahim N. Hajj (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Postroute gate sizing for crosstalk noise reduction. - Murat R. Becer; David T. Blaauw; Ilan Algor; Rajendran Panda; Chanhee Oh; Vladimir Zolotov; Ibrahim N. Hajj (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Extended Nodal Analysis. - Ibrahim N. Hajj (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

On Device Modeling for Circuit Simulation With Application to Carbon-Nanotube and Graphene Nano-Ribbon Field-Effect Transistors. - Ibrahim N. Hajj (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Beyond SPICE. - Ibrahim N. Hajj (ISCAS, 2017)