Gate Matrix Layout Synthesis with Two-Dimensional Folding. - Ichiang Lin; David Hung-Chang Du; Steve H.-C. Yen (DAC, 1989)

Performance-Driven Constructive Placement. - Ichiang Lin; David Hung-Chang Du (DAC, 1990)

Analyzing Cycle Stealing on Synchronous Circuits with Level-Sensitive Latches. - Ichiang Lin; John A. Ludwig; Kwok Eng (DAC, 1992)

On Wafer-Packing Problems. - David Hung-Chang Du; Ichiang Lin; K. C. Chang 001 (IEEE Trans. Computers, 1993)

Timing verification of dynamic circuits. - Kumar Venkat; Liang Chen; Ichiang Lin; Piyush Mistry; Pravin Madhani (IEEE J. Solid State Circuits, 1996)

Timing Challenges for Very Deep Sub-Micron (VDSM) IC. - Ichiang Lin; Chien-In Henry Chen (VLSI Design, 2002)