A 5-V single-chip delta-sigma audio A/D converter with 111 dB dynamic range. - Ichiro Fujimori; Kazuo Koyama; David Trager; Fred Tam; Lorenzo Longo (IEEE J. Solid State Circuits, 1997)

A 1.5 V, 4.1 mW dual-channel audio delta-sigma D/A converter. - Ichiro Fujimori; Tetsuro Sugimoto (IEEE J. Solid State Circuits, 1998)

A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8× oversampling ratio. - Ichiro Fujimori; Lorenzo Longo; Armond Hairapetian; Kazushi Seiyama; Steve Kosic; Jun Cao 001; Shu-Lap Chan (IEEE J. Solid State Circuits, 2000)

A multibit delta-sigma audio DAC with 120-dB dynamic range. - Ichiro Fujimori; Akihiko Nogi; Tetsuro Sugimoto (IEEE J. Solid State Circuits, 2000)

A fully integrated SONET OC-48 transceiver in standard CMOS. - Afshin Momtaz; Jun Cao 001; Mario Caresosa; Armond Hairapetian; David Chung; Kambiz Vakilian; Michael M. Green; Wee-Guan Tan; Keh-Chee Jen; Ichiro Fujimori; Yijun Cai (IEEE J. Solid State Circuits, 2001)

OC-192 transmitter and receiver in standard 0.18-μm CMOS. - Jun Cao 001; Michael M. Green; Afshin Momtaz; Kambiz Vakilian; David Chung; Keh-Chee Jen; Mario Caresosa; Xin Wang; Wee-Guan Tan; Yijun Cai; Ichiro Fujimori; Armond Hairapetian (IEEE J. Solid State Circuits, 2002)

A Fully Integrated 10-Gb/s Receiver With Adaptive Optical Dispersion Equalizer in 0.13-µm CMOS. - Afshin Momtaz; David Chung; Namik Kocaman; Jun Cao 001; Mario Caresosa; Bo Zhang 029; Ichiro Fujimori (IEEE J. Solid State Circuits, 2007)

21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber. - Jun Cao 001; Bo Zhang 029; Ullas Singh; Delong Cui; Anand Vasani; Adesh Garg; Wei Zhang; Namik Kocaman; Deyi Pi; Bharath Raghavan; Hui Pan 002; Ichiro Fujimori; et al. (ISSCC, 2009)

A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber. - Jun Cao 001; Bo Zhang 029; Ullas Singh; Delong Cui; Anand Vasani; Adesh Garg; Wei Zhang; Namik Kocaman; Deyi Pi; Bharath Raghavan; Hui Pan 002; Ichiro Fujimori; et al. (IEEE J. Solid State Circuits, 2010)

A digital wideband CDR with ±15.6kppm frequency tracking at 8Gb/s in 40nm CMOS. - Hui Pan 002; Magesh Valliappan; Wei Zhang; Kambiz Vakilian; Seong-Ho Lee; Hamid Hatamkhani; Mario Caresosa; Karo Khanoyan; Haitao Tong; Duke Tran; Anthony Brewster; Ichiro Fujimori (ISSCC, 2011)

Optical PCB interconnects, Niche or mainstream? - Ichiro Fujimori; SeongHwan Cho; Joshua Friedrich; John T. Stonick (ISSCC, 2012)

F3: Emerging technologies for wireline communication. - Elad Alon; Azita Emami; Gerrit den Besten; Ichiro Fujimori; Tadahiro Kuroda; Masafumi Nogawa; Hisakatsu Yamaguchi (ISSCC, 2013)

Session 7 overview: Optical transceivers and silicon photonics. - Ichiro Fujimori; Masafumi Nogawa (ISSCC, 2013)

8.6 A full-duplex line driver for Gigabit Ethernet with rail-to-rail class-AB output stage in 28nm CMOS. - Hui Pan 002; Yuan Yao; Mostafa Hammad; Junhua Tan; Karim Abdelhalim; Evelyn Wenting Wang; Rick C. J. Hsu; Jenny Yu; Joseph N. Y. Aziz; Derek Tam; Ichiro Fujimori (ISSCC, 2014)

A 2.7GHz to 7GHz fractional-N LCPLL utilizing multimetal layer SoC technology in 28nm CMOS. - Chang-Hyeon Lee; Lindel Kabalican; Yan Ge; Hendra Kwantono; Greg Unruh; Mark Chambers; Ichiro Fujimori (VLSIC, 2014)

A Full-Duplex Line Driver for Gigabit Ethernet With Rail-to-Rail Class-AB Output Stage in 28 nm CMOS. - Hui Pan 002; Yuan Yao; Mostafa Hammad; Junhua Tan; Karim Abdelhalim; Evelyn Wenting Wang; Rick C. J. Hsu; Derek Tam; Ichiro Fujimori (IEEE J. Solid State Circuits, 2014)

F1: High-speed interleaved ADCs. - Stephane Le Tuai; Borivoje Nikolic; Tetsuya Iizuka; Ichiro Fujimori (ISSCC, 2015)

A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS. - Chang-Hyeon Lee; Lindel Kabalican; Yan Ge; Hendra Kwantono; Greg Unruh; Mark Chambers; Ichiro Fujimori (IEEE J. Solid State Circuits, 2015)

A 28 Gb/s Multistandard Serial Link Transceiver for Backplane Applications in 28 nm CMOS. - Bo Zhang 029; Karapet Khanoyan; Hamid Hatamkhani; Haitao Tong; Kangmin Hu; Siavash Fallahi; Mohammed M. Abdul-Latif; Kambiz Vakilian; Ichiro Fujimori; Anthony Brewster (IEEE J. Solid State Circuits, 2015)

19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC. - Fazil Ahmad; Greg Unruh; Amrutha Iyer; Pin-En Su; Sherif Abdalla; Bo Shen; Mark Chambers; Ichiro Fujimori (ISSCC, 2016)

F4: Emerging short-reach and high-density interconnect solutions for internet of everything. - Ichiro Fujimori; Martin Brox; Elad Alon; Pavan Kumar Hanumolu; Gerrit den Besten; Hideyuki Nosaka (ISSCC, 2016)

10.3 An analog front-end for 100BASE-T1 automotive Ethernet in 28nm CMOS. - Hui Pan 002; Junhua Tan; Evelyn Wenting Wang; Jingguang Wang; Karthik Swaminathan; Ramalingam Pandarinathan; Ramesh Pasagadugula; VamshiKrishna Yakkala; Mostafa Hammad; Karim Abdelhalim; Kaijun Li; Su Cui; et al. (ISSCC, 2016)

F5: Wireline transceivers for Mega Data Centers: 50Gb/s and beyond. - Yohan Frans; Ichiro Fujimori; Seung-Jun Bae; Samuel Palermo; Hideyuki Nosaka; Simone Erba (ISSCC, 2017)

EE4: Semiconductor economics: How business decisions are engineered. - Ichiro Fujimori; Pavan Kumar Hanumolu (ISSCC, 2017)

A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling. - Fazil Ahmad; Greg Unruh; Amrutha Iyer; Pin-En Su; Sherif Abdalla; Bo Shen; Mark Chambers; Ichiro Fujimori (IEEE J. Solid State Circuits, 2017)