0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier. - Toshikazu Suzuki; Yoshinobu Yamagami; Ichiro Hatanaka; Akinori Shibayama; Hironori Akamatsu; Hiroyuki Yamauchi (IEICE Trans. Electron., 2005)

A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme. - Toshikazu Suzuki; Yoshinobu Yamagami; Ichiro Hatanaka; Akinori Shibayama; Hironori Akamatsu; Hiroyuki Yamauchi (IEEE J. Solid State Circuits, 2006)