A CCITT standard 32 kbps ADPCM LSI codec. - Takao Nishitani; Ichiro Kuroda; Masao Satoh; Tadaharu Katoh; Reiichi Fukuda; Yasushi Aoki (ICASSP, 1985)

Advanced single-chip signal processor. - Takao Nishitani; Ichiro Kuroda; Yuichi Kawakami; H. Tanaka; Tom Nukiyama (ICASSP, 1986)

Blockdiagram programming system for 32 bit floating point signal processor. - Ichiro Kuroda; Takao Nishitani; Teiji Takeuchi; Hitoshi Koyama; Junko Sunaga; Shuji Matsukawa (ICASSP, 1987)

A CCITT standard 32 kbit/s ADPCM LSI codec. - Takao Nishitani; Ichiro Kuroda; Masao Satoh; Tadaharu Katoh; Yasuo Aoki (IEEE Trans. Acoust. Speech Signal Process., 1987)

A reconfigurable processor array with routing LSIs and general purpose DSPs. - Jacob Levison; Ichiro Kuroda; Takao Nishitani (ASAP, 1992)

Asynchronous multirate system design for programmable DSPs. - Ichiro Kuroda; Takao Nishitani (ICASSP, 1992)

Low-power multimedia RISC. - Kouhei Nadehara; Ichiro Kuroda; Masayuki Daito; Takashi Nakayama (IEEE Micro, 1995)

A fast full-search motion estimation method for programmable processors with a multiply-accumulator. - Yukihiro Naito; Takashi Miyazaki; Ichiro Kuroda (ICASSP, 1996)

Code positioning to reduce instruction cache misses in signal processing applications on multimedia RISC processors. - Hans-Joachim Stolberg; Masao Ikekawa; Ichiro Kuroda (ICASSP, 1997)

Fast 2D IDCT implementation with multimedia instructions for a software MPEG2 decoder. - Eri Murata; Masao Ikekawa; Ichiro Kuroda (ICASSP, 1998)

Software MPEG-2 video decoder on a 200-MHz, low-power multimedia microprocessor. - Kouhei Nadehara; Hanno Lieske; Ichiro Kuroda (ICASSP, 1998)

H.263 mobile video codec based on a low power consumption digital signal processor. - Yukihiro Naito; Ichiro Kuroda (ICASSP, 1998)

Low-energy heterogeneous digit-serial Reed-Solomon codecs. - Leilei Song; Keshab K. Parhi; Ichiro Kuroda; Takao Nishitani (ICASSP, 1998)

An 800-MOPS, 110-mW, 1.5-V, parallel DSP for mobile multimedia processing. - Hiroyuki Igura; Yukihiro Naito; Kenya Kazama; Ichiro Kuroda; Masato Motomura; Masakazu Yamashina (IEEE J. Solid State Circuits, 1998)

V830R/AV: embedded multimedia superscalar RISC processor. - Kazumasa Suzuki; Tomohisa Arai; Kouhei Nadehara; Ichiro Kuroda (IEEE Micro, 1998)

Multimedia processors. - Ichiro Kuroda; Takao Nishitani (Proc. IEEE, 1998)

Radix-4 FFT implementation using SIMD multimedia instructions. - Kouhei Nadehara; Takashi Miyazaki; Ichiro Kuroda (ICASSP, 1999)

A 2000-MOPS embedded RISC processor with a Rambus DRAM controller. - Kazumasa Suzuki; Masayuki Daito; Tomoo Inoue; Kouhei Nadehara; Masahiro Nomura; Masayuki Mizuno; Tomofumi Iima; Shoichiro Sato; Terumi Fukuda; Tomohisa Arai; Ichiro Kuroda; Masakazu Yamashina (IEEE J. Solid State Circuits, 1999)

Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs. - Leilei Song; Keshab K. Parhi; Ichiro Kuroda; Takao Nishitani (IEEE Trans. Very Large Scale Integr. Syst., 2000)

A low-power programmable DSP core architecture for 3G mobile terminals. - Takahiro Kumura; Daiji Ishii; Masao Ikekawa; Ichiro Kuroda; Makoto Yoshida (ICASSP, 2001)

Multimedia Signal Processor For Mobile Applications. - Masao Ikekawa; M. Hori; Kouhei Nadehara; Takahiro Kumura; Makoto Yoshida; Ichiro Kuroda; Takao Nishitani (ICME, 2001)

Guest Editors' Introduction. - Liang-Gee Chen; Hsueh-Ming Hang; Ichiro Kuroda (J. VLSI Signal Process., 2001)

Real-Time Software Video Codec with a Fast Adaptive Motion Vector Search. - Tatsuji Moriyoshi; Hiroshi Shinohara; Takashi Miyazaki; Ichiro Kuroda (J. VLSI Signal Process., 2001)

MPEG-2 AAC 5.1-Channel Decoder Software for a Low-Power Embedded RISC Microprocessor. - Yuichiro Takamizawa; Kouhei Nadehara; Max Boegli; Masao Ikekawa; Ichiro Kuroda (J. VLSI Signal Process., 2001)

Asynchronous Multirate Real-Time Scheduling for Programmable DSPs. - Ichiro Kuroda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

VLIW DSP for mobile applications. - Takahiro Kumura; Masao Ikekawa; Makoto Yoshida; Ichiro Kuroda (IEEE Signal Process. Mag., 2002)

Optimization of decision-timing for early termination of SSDA-based block matching. - Atsushi Hatabu; Takashi Miyazaki; Ichiro Kuroda (ICASSP (2), 2003)

A 51.2-GOPS scalable video recognition processor for intelligent cruise control based on a linear array of 128 four-way VLIW processing elements. - Shorin Kyo; Takuya Koga; Shin'ichiro Okazaki; Ichiro Kuroda (IEEE J. Solid State Circuits, 2003)

A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication. - Yuichi Nakamura 002; Kohei Hosokawa; Ichiro Kuroda; Ko Yoshikawa; Takeshi Yoshimura (DAC, 2004)

A 51.2 GOPS Programmable Video Recognition Processor for Vision-Based Intelligent Cruise Control Applications. - Shorin Kyo; Takuya Koga; Shin'ichiro Okazaki; Ichiro Kuroda (IEICE Trans. Inf. Syst., 2004)

Fast and accurate motion estimation algorithm by adaptive search range and shape selection. - Toru Yamada; Masao Ikekawa; Ichiro Kuroda (ICASSP (2), 2005)

Performance Evaluation of the AV CODEC on a Low-Power SPXK5SC DSP Core. - Takahiro Kumura; Norio Kayama; Shinichi Shionoya; Kazuo Kumagiri; Takao Kusano; Makoto Yoshida; Masao Ikekawa; Ichiro Kuroda; Takao Nishitani (IEICE Trans. Inf. Syst., 2005)

QVGA/CIF Resolution MPEG-4 Video Codec Based on a Low-Power and General-Purpose DSP. - Atsushi Hatabu; Takashi Miyazaki; Ichiro Kuroda (J. VLSI Signal Process., 2005)

Special Section on Papers Selected from the 20th Symposium on Signal Processing. - Ichiro Kuroda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Media Processing LSI Architectures for Automotives - Challenges and Future Trends - . - Ichiro Kuroda; Shorin Kyo (IEICE Trans. Electron., 2007)

Special Section on Signal Processing for Audio and Visual Systems and Its Implementations. - Ichiro Kuroda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)