Video signal processor configuration by multiprocessor approach. - Takao Nishitani; Ichiro Tamitani; Hidenobu Harasaki; Masakatsu Yamashina; Tadayoshi Enomoto (ICASSP, 1986)

Realtime video signal processor module. - Hidenobu Harasaki; Ichiro Tamitani; Yukio Endo; Takao Nishitani; Masakatsu Yamashina; Tadayoshi Enomoto; Norio Suzuki (ICASSP, 1987)

A single-board video signal processor module employing newly developed LSI devices. - Hidenobu Harasaki; Ichiro Tamitani; Yukio Endo; Takao Nishitani; Masakatsu Yamashina; Tadayoshi Enomoto; Norio Suzuki (IEEE J. Sel. Areas Commun., 1988)

A microprogrammable real-time video signal processor (VSP) for motion compensation. - Masakazu Yamashina; Tadayoshi Enomoto; Takemitsu Kunio; Ichiro Tamitani; Hidenobu Harasaki; Yukio Endo; Takao Nishitani; Masao Satoh; Koichi Kikuchi (IEEE J. Solid State Circuits, 1988)

Parallel video signal processor configuration based on overlap-save technique and its LSI processor element: VISP. - Takao Nishitani; Ichiro Tamitani; Hidenobu Harasaki; Yukio Endo; Toshiyuki Kanou; Koichi Kikuchi (J. VLSI Signal Process., 1989)

A real-time software programmable processor for HDTV and stereo scope signals. - Takao Nishitani; Ichiro Tamitani; Hidenobu Harasaki; Mitsuharu Yano (ASAP, 1990)

A real-time HDTV signal processor: HD-VSP. - Ichiro Tamitani; Hidenobu Harasaki; Takao Nishitani (IEEE Trans. Circuits Syst. Video Technol., 1991)

An encoder/decoder chip set for the MPEG video standard. - Ichiro Tamitani; Mutsumi Ohta; Yasushi Ooi; Akio Yoshida; Mamoru Nomura; Hitoshi Koyama; Takao Nishitani (ICASSP, 1992)

An MPEG-2 encoder architecture based on a single-chip dedicated LSI with a control MPU. - Yasushi Ooi; Osamu Ohnishi; Yutaka Yokoyama; Yoichi Katayama; Masayuki Mizuno; Masakazu Yamashina; Hideo Takano; Naoya Hayashi; Ichiro Tamitani (ICASSP, 1997)

A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking. - Masayuki Mizuno; Yasushi Ooi; Naoya Hayashi; Junichi Goto; Masatoshi Hozumi; Koichiro Furuta; Atsufumi Shibayama; Yoetsu Nakazawa; Osamu Ohnishi; Shu-Yu Zhu; Yutaka Yokoyama; Yoichi Katayama; et al. (IEEE J. Solid State Circuits, 1997)