An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor. - Idris Somoye; Jim Plusquellic; Tom J. Mannos; Brian Dziki (Cryptogr., 2024)

Self-Assertion-Based Countermeasures Within a RISC-V Microprocessor for Coverage of Information Leakage Faults. - Idris Somoye; Tom J. Mannos; Brian Dziki; Jim Plusquellic (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)