Test Time Reduction of 3-D Stacked ICs Using Ternary Coded Simultaneous Bidirectional Signaling in Parallel Test Ports. - Iftikhar A. Soomro; Mohammad Samie; Ian K. Jennions (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Reduced Pin-Count Test Strategy for 3D Stacked ICs Using Simultaneous Bi-Directional Signaling Based Time Division Multiplexing. - Iftikhar A. Soomro; Mohammad Samie; Ian K. Jennions (IEEE Access, 2021)