Design and Implementation of an FPGA-Based 1.452-Gbps Non-pipelined AES Architecture. - Ignacio Algredo-Badillo; Claudia Feregrino Uribe; René Cumplido (ICCSA (3), 2006)

FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks. - Ignacio Algredo-Badillo; Claudia Feregrino Uribe; René Cumplido; Miguel Morales-Sandoval (ReConFig, 2008)

Design and Implementation of a Non-pipelined MD5 Hardware Architecture Using a New Functional Description. - Ignacio Algredo-Badillo; Claudia Feregrino Uribe; René Cumplido; Miguel Morales-Sandoval (IEICE Trans. Inf. Syst., 2008)

A Run Time Reconfigurable Co-processor for Elliptic Curve Scalar Multiplication. - Miguel Morales-Sandoval; Claudia Feregrino Uribe; René Cumplido; Ignacio Algredo-Badillo (ENC, 2009)

An area/performance trade-off analysis of a GF(2m) multiplier architecture for elliptic curve cryptography. - Miguel Morales-Sandoval; Claudia Feregrino Uribe; René Cumplido; Ignacio Algredo-Badillo (Comput. Electr. Eng., 2009)

Efficient hardware architecture for the AES-CCM protocol of the IEEE 802.11i standard. - Ignacio Algredo-Badillo; Claudia Feregrino Uribe; René Cumplido; Miguel Morales-Sandoval (Comput. Electr. Eng., 2010)

A Single Formula and its Implementation in FPGA for Elliptic Curve Point Addition Using Affine Representation. - Miguel Morales-Sandoval; Claudia Feregrino Uribe; René Cumplido; Ignacio Algredo-Badillo (J. Circuits Syst. Comput., 2010)

Novel Hardware Architecture for Implementing the Inner Loop of the SHA-2 Algorithms. - Ignacio Algredo-Badillo; Claudia Feregrino Uribe; René Cumplido; Miguel Morales-Sandoval (DSD, 2011)

Throughput and Efficiency Analysis of Unrolled Hardware Architectures for the SHA-512 Hash Algorithm. - Ignacio Algredo-Badillo; Miguel Morales-Sandoval; Claudia Feregrino Uribe; René Cumplido (ISVLSI, 2012)

A Lossless Data Hiding Technique based on AES-DWT - Francisco Rubén Castillo Soria; Gustavo Fernández Torres; Ignacio Algredo-Badillo (CoRR, 2012)

Performance Analysis of ANFIS in short term Wind Speed Prediction - Ernesto Cortés Pérez; Ignacio Algredo-Badillo; Víctor Hugo García Rodríguez (CoRR, 2012)

A programmable FPGA-based cryptoprocessor for bilinear pairings over F2m. - Eduardo Cuevas-Farfan; Miguel Morales-Sandoval; René Cumplido; Claudia Feregrino Uribe; Ignacio Algredo-Badillo (ReCoSoC, 2013)

FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256. - Ignacio Algredo-Badillo; Claudia Feregrino Uribe; René Cumplido; Miguel Morales-Sandoval (Microprocess. Microsystems, 2013)

A compact FPGA-based processor for the Secure Hash Algorithm SHA-256. - Rommel García; Ignacio Algredo-Badillo; Miguel Morales-Sandoval; Claudia Feregrino Uribe; René Cumplido (Comput. Electr. Eng., 2014)

A comparative study of the wavenet PID controllers for applications in non-linear systems. - M. A. Saldaña-O.; Luis Enrique Ramos-Velasco; J. P. Ordaz-O.; Abel García-Barrientos; Ignacio Algredo-Badillo; Jean-François Balmat; Frédéric Lafont (CCE, 2015)

A compact FPGA-based microcoded coprocessor for exponentiation in asymmetric encryption. - Luis Armando Rodriguez Flores; Miguel Morales-Sandoval; René Cumplido; Claudia Feregrino Uribe; Ignacio Algredo-Badillo (LASCAS, 2017)

Lightweight Security Hardware Architecture Using DWT and AES Algorithms. - Ignacio Algredo-Badillo; Francisco Rubén Castillo Soria; Kelsey A. Ramírez-Gutiérrez; Luis Alberto Morales-Rosales; Alejandro Medina-Santiago; Claudia Feregrino Uribe (IEICE Trans. Inf. Syst., 2018)

On-road obstacle detection video system for traffic accident prevention. - Luis Alberto Morales-Rosales; Ignacio Algredo-Badillo; Carlos Arturo Hernández-Gracidas; Héctor Rodríguez Rangel; Mariana Lobato Báez (J. Intell. Fuzzy Syst., 2018)

Reconfigurable arithmetic logic unit designed with threshold logic gates. - Alejandro Medina-Santiago; Mario Alfredo Reyes-Barranca; Ignacio Algredo-Badillo; Alfonso Martinez Cruz; Kelsey A. Ramírez-Gutiérrez; Eleazar Adrián Cortés-Barrón (IET Circuits Devices Syst., 2019)

Real time FPGA-ANN architecture for outdoor obstacle detection focused in road safety. - Ignacio Algredo-Badillo; Luis Alberto Morales-Rosales; Carlos Arturo Hernández-Gracidas; Juan C. Cruz-Victoria; Daniel Pacheco Bautista; Miguel Morales-Sandoval (J. Intell. Fuzzy Syst., 2019)

A fuzzy petri net model for assessing analogical reasoning in children ranging from 5 to 8 years old. - Luis Alberto Morales-Rosales; Ignacio Algredo-Badillo; Mariana Lobato Báez; Carlos Arturo Hernández-Gracidas; Héctor Rodríguez Rangel (J. Intell. Fuzzy Syst., 2020)

A Metaheuristic Optimization Approach for Parameter Estimation in Arrhythmia Classification from Unbalanced Data. - Juan Carlos Carrillo-Alarcón; Luis Alberto Morales-Rosales; Héctor Rodríguez Rangel; Mariana Lobato Báez; Antonio Muñoz 004; Ignacio Algredo-Badillo (Sensors, 2020)

Bit-Vector-Based Hardware Accelerator for DNA Alignment Tools. - Daniel Pacheco Bautista; Ricardo Carreño Aguilera; Francisco Aguilar Acevedo; Ignacio Algredo-Badillo (J. Circuits Syst. Comput., 2021)

A Compact FPGA-Based Accelerator for Curve-Based Cryptography in Wireless Sensor Networks. - Miguel Morales-Sandoval; Luis Armando Rodriguez Flores; René Cumplido; Jose Juan Garcia-Hernandez; Claudia Feregrino; Ignacio Algredo-Badillo (J. Sensors, 2021)

Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES. - Ignacio Algredo-Badillo; Kelsey A. Ramírez-Gutiérrez; Luis Alberto Morales-Rosales; Daniel Pacheco Bautista; Claudia Feregrino Uribe (Sensors, 2021)

CMOS Implementation of ANNs Based on Analog Optimization of N-Dimensional Objective Functions. - Alejandro Medina-Santiago; Carlos Arturo Hernández-Gracidas; Luis Alberto Morales-Rosales; Ignacio Algredo-Badillo; Monica Amador García; Jorge Antonio Orozco Torres (Sensors, 2021)

Irregularities recognition system for automotive pieces. - Ignacio Algredo-Badillo; Germàn Portillo-García; Kelsey A. Ramírez-Gutiérrez; Luis Alberto Morales-Rosales (Int. J. Comput. Vis. Robotics, 2022)

A SHA-256 Hybrid-Redundancy Hardware Architecture for Detecting and Correcting Errors. - Ignacio Algredo-Badillo; Miguel Morales-Sandoval; Alejandro Medina-Santiago; Carlos Arturo Hernández-Gracidas; Mariana Lobato Báez; Luis Alberto Morales-Rosales (Sensors, 2022)

Trade-Off Analysis of Hardware Architectures for Channel-Quality Classification Models. - Alan Torres-Alvarado; Luis Alberto Morales-Rosales; Ignacio Algredo-Badillo; Francisco López-Huerta; Mariana Lobato Báez; Juan Carlos López Pimentel (Sensors, 2022)

An SHA-3 Hardware Architecture against Failures Based on Hamming Codes and Triple Modular Redundancy. - Alan Torres-Alvarado; Luis Alberto Morales-Rosales; Ignacio Algredo-Badillo; Francisco López-Huerta; Mariana Lobato Báez; Juan Carlos López Pimentel (Sensors, 2022)

White-Box Adversarial Attacks Against Sentiment-Analysis Models using an Aspect-Based Approach. - Monserrat Vázquez-Hernández; Ignacio Algredo-Badillo; Luis Alberto Morales-Rosales; Luis Villaseñor Pineda (CISETC, 2023)

Biometric lock with facial recognition implemented with deep learning techniques. - José Misael Burruel-Zazueta; Héctor Rodríguez Rangel; Gloria Ekaterine Peralta-Peñuñuri; Vicenç Puig Cayuela; Ignacio Algredo-Badillo; Luis Alberto Morales-Rosales (Comput. Sci. Inf. Syst., 2024)