Reseeding using compaction of pre-generated LFSR sub-sequences. - Artur Jutman; Igor Aleksejev; Jaan Raik; Raimund Ubar (ICECS, 2008)

Fast extended test access via JTAG and FPGAs. - Sergei Devadze; Artur Jutman; Igor Aleksejev; Raimund Ubar (ITC, 2009)

Turning JTAG inside out for fast extended test access. - Sergei Devadze; Artur Jutman; Igor Aleksejev; Raimund Ubar (LATW, 2009)

Invited paper: System-wide fault management based on IEEE P1687 IJTAG. - Artur Jutman; Sergei Devadze; Igor Aleksejev (ReCoSoC, 2011)

Embedded synthetic instruments for Board-Level testing. - Artur Jutman; Sergei Devadze; Igor Aleksejev; Thomas Wenzel (ETS, 2012)

FPGA-based synthetic instrumentation for board test. - Igor Aleksejev; Artur Jutman; Sergei Devadze; Sergei Odintsov; Thomas Wenzel (ITC, 2012)

Virtual reconfigurable scan-chains on FPGAs for optimized board test. - Igor Aleksejev; Sergei Devadze; Artur Jutman; Konstantin Shibin (LATS, 2015)

Complex delay fault reasoning with sequential 7-valued algebra. - Jaak Kousaar; Raimund Ubar; Igor Aleksejev (LATS, 2015)

On coverage of timing related faults at board level. - Artur Jutman; Igor Aleksejev; Sergei Devadze (ETS, 2016)

Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures. - Igor Aleksejev; Sergei Devadze; Artur Jutman; Konstantin Shibin (J. Electron. Test., 2016)

Run-time reconfigurable instruments for advanced board-level testing. - Igor Aleksejev; Artur Jutman; Sergei Devadze (IEEE Instrum. Meas. Mag., 2017)