Modified Approach to Automata State Encoding for LUT FPGA Implementation. - Igor Lemberski (EUROMICRO, 1998)

XILINX4000 Architecture-Driven Synthesis for Speed. - Igor Lemberski; M. Ratniece (FPL, 1998)

Methodology of Logic Synthesis for Implementation Using Heterogeneous LUT FPGAs. - Igor Lemberski (Great Lakes Symposium on VLSI, 1999)

Optimal Two-Level Delay - Insensitive Implementation of Logic Functions. - Igor Lemberski; Mark B. Josephs (PATMOS, 2002)

Cost Effective Implementation of Asynchronous Two-Level Logic. - Igor Lemberski (World Congress on Engineering, 2007)

Avoiding Hazards for Speed-Independent Logic Design. - Igor Lemberski (World Congress on Engineering, 2007)

Asynchronous two-level logic of reduced cost. - Igor Lemberski; Petr Fiser (DDECS, 2009)

Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints. - Igor Lemberski; Petr Fiser (DSD, 2010)

Asynchronous sum-of-products logic minimization and orthogonalization. - Igor Lemberski; Petr Fiser; Ruslan Suleimanov (Int. J. Circuit Theory Appl., 2014)

Dual-rail asynchronous logic multi-level implementation. - Igor Lemberski; Petr Fiser (Integr., 2014)

Literal Decomposition for LUT-Oriented Asynchronous Dual-Rail Logic Synthesis. - Igor Lemberski (J. Circuits Syst. Comput., 2015)

Asynchronous Logic Implementation Based on Factorized DIMS. - Igor Lemberski (J. Circuits Syst. Comput., 2017)

Asynchronous logic design targeting LUTs. - Igor Lemberski; Artjoms Suponenkovs (MECO, 2018)

Asynchronous logiс one-level LUT design based on partial acknowledgement. - Igor Lemberski; Artjoms Suponenkovs (Microelectron. J., 2018)

LUT-Oriented Asynchronous Logic Design Based on Resubstitution. - Igor Lemberski; Artjoms Suponenkovs; Marina Uhanova (DTIS, 2019)

Resubstitution method for big size Boolean logic design targeting look-up-table implementation. - Igor Lemberski; Artjoms Suponenkovs (Int. J. Circuit Theory Appl., 2021)