Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow. - Igor Loi; Federico Angiolini; Luca Benini (Nano-Net, 2007)

Area and Power Modeling for Networks-on-Chip with Layout Awareness. - Paolo Meloni; Igor Loi; Federico Angiolini; Salvatore Carta; Massimo Barbaro; Luigi Raffo; Luca Benini (VLSI Design, 2007)

Developing Mesochronous Synchronizers to Enable 3D NoCs. - Igor Loi; Federico Angiolini; Luca Benini (DATE, 2008)

A low-overhead fault tolerance scheme for TSV-based 3D network on chip links. - Igor Loi; Subhasish Mitra; Thomas H. Lee; Shinobu Fujita; Luca Benini (ICCAD, 2008)

Synthesis of low-overhead configurable source routing tables for network interfaces. - Igor Loi; Federico Angiolini; Luca Benini (DATE, 2009)

An efficient distributed memory interface for many-core platform with 3D stacked DRAM. - Igor Loi; Luca Benini (DATE, 2010)

A new physical routing approach for robust bundled signaling on NoC links. - Mohammad Reza Kakoee; Igor Loi; Luca Benini (ACM Great Lakes Symposium on VLSI, 2010)

3D NoCs - Unifying inter & intra chip communication. - Igor Loi; Pol Marchal; Antonio Pullini; Luca Benini (ISCAS, 2010)

A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters. - Abbas Rahimi; Igor Loi; Mohammad Reza Kakoee; Luca Benini (DATE, 2011)

Design space exploration for 3D-stacked DRAMs. - Christian Weis; Norbert Wehn; Igor Loi; Luca Benini (DATE, 2011)

Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing. - Ahmed Yasir Dogan; David Atienza; Andreas Burg 001; Igor Loi; Luca Benini (PATMOS, 2011)

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. - Geert Van der Plas; Paresh Limaye; Igor Loi; Abdelkarim Mercha; Herman Oprins; Cristina Torregiani; Steven Thijs; Dimitri Linten; Michele Stucchi; Guruprasad Katti; Dimitrios Velenis; Vladimir Cherman; et al. (IEEE J. Solid State Circuits, 2011)

Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip. - Igor Loi; Federico Angiolini; Shinobu Fujita; Subhasish Mitra; Luca Benini (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

A resilient architecture for low latency communication in shared-L1 processor clusters. - Mohammad Reza Kakoee; Igor Loi; Luca Benini (DATE, 2012)

An energy efficient DRAM subsystem for 3D integrated SoCs. - Christian Weis; Igor Loi; Luca Benini; Norbert Wehn (DATE, 2012)

3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory. - Giulia Beanato; Igor Loi; Giovanni De Micheli; Yusuf Leblebici; Luca Benini (VLSI-SoC, 2012)

Configurable Low-Latency Interconnect for Multi-core Clusters. - Giulia Beanato; Igor Loi; Giovanni De Micheli; Yusuf Leblebici; Luca Benini (VLSI-SoC (Selected Papers), 2012)

Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters. - Mohammad Reza Kakoee; Igor Loi; Luca Benini (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A high-performance multiported L2 memory IP for scalable three-dimensional integration. - Erfan Azarkhish; Igor Loi; Luca Benini (3DIC, 2013)

A shared-FPU architecture for ultra-low power MPSoCs. - Mohammad Reza Kakoee; Igor Loi; Luca Benini (Conf. Computing Frontiers, 2013)

3D logarithmic interconnect: Stacking multiple L1 memory dies over multi-core clusters. - Erfan Azarkhish; Igor Loi; Luca Benini (NOCS, 2013)

A case for three-dimensional stacking of tightly coupled data memories over multi-core clusters using low-latency interconnects. - Erfan Azarkhish; Igor Loi; Luca Benini (IET Comput. Digit. Tech., 2013)

Exploration and Optimization of 3-D Integrated DRAM Subsystems. - Christian Weis; Igor Loi; Luca Benini; Norbert Wehn (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Ultra-low-latency lightweight DMA for tightly coupled multi-core clusters. - Davide Rossi; Igor Loi; Germain Haugou; Luca Benini (Conf. Computing Frontiers, 2014)

A multi banked - Multi ported - Non blocking shared L2 cache for MPSoC platforms. - Igor Loi; Luca Benini (DATE, 2014)

A Stream Buffer Mechanism for Pervasive Splitting Transformations on Polyhedral Process Networks. - Paolo Meloni; Giuseppe Tuveri; Luigi Raffo; Igor Loi; Francesco Conti 001 (MES, 2014)

Online process transformation for polyhedral process networks in shared-memory MPSoCs. - Paolo Meloni; Giuseppe Tuveri; Luigi Raffo; Igor Loi; Francesco Conti 001 (MECO, 2014)

Energy-efficient vision on the PULP platform for ultra-low power parallel computing. - Francesco Conti 001; Davide Rossi; Antonio Pullini; Igor Loi; Luca Benini (SiPS, 2014)

Exploring multi-banked shared-L1 program cache on ultra-low power, tightly coupled processor clusters. - Igor Loi; Davide Rossi; Germain Haugou; Michael Gautschi; Luca Benini (Conf. Computing Frontiers, 2015)

High performance AXI-4.0 based interconnect for extensible smart memory cubes. - Erfan Azarkhish; Davide Rossi; Igor Loi; Luca Benini (DATE, 2015)

PULP: A parallel ultra low power platform for next generation IoT applications. - Davide Rossi; Francesco Conti 001; Andrea Marongiu; Antonio Pullini; Igor Loi; Michael Gautschi; Giuseppe Tagliavini; Alessandro Capotondi; Philippe Flatresse; Luca Benini (Hot Chips Symposium, 2015)

A Modular Shared L2 Memory Design for 3-D Integration. - Erfan Azarkhish; Davide Rossi; Igor Loi; Luca Benini (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Design and Evaluation of a Processing-in-Memory Architecture for the Smart Memory Cube. - Erfan Azarkhish; Davide Rossi; Igor Loi; Luca Benini (ARCS, 2016)

Curbing the roofline: a scalable and flexible architecture for CNNs on FPGA. - Paolo Meloni; Gianfranco Deriu; Francesco Conti 001; Igor Loi; Luigi Raffo; Luca Benini (Conf. Computing Frontiers, 2016)

193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. - Davide Rossi; Antonio Pullini; Igor Loi; Michael Gautschi; Frank Kagan Gürkaynak; Adam Teman; Jeremy Constantin; Andreas Burg 001; Ivan Miro Panades; Edith Beigné; Fabien Clermidy; Fady Abouzeid; et al. (COOL Chips, 2016)

A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision. - Antonio Pullini; Francesco Conti 001; Davide Rossi; Igor Loi; Michael Gautschi; Luca Benini (ISCAS, 2016)

A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC. - Paolo Meloni; Gianfranco Deriu; Francesco Conti 001; Igor Loi; Luigi Raffo; Luca Benini (ReConFig, 2016)

On-the-fly adaptivity for process networks over shared-memory platforms. - Giuseppe Tuveri; Paolo Meloni; Francesca Palumbo; Giovanni Pietro Seu; Igor Loi; Francesco Conti 001; Luigi Raffo (Microprocess. Microsystems, 2016)

PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision. - Francesco Conti 001; Davide Rossi; Antonio Pullini; Igor Loi; Luca Benini (J. Signal Process. Syst., 2016)

A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors. - Davide Rossi; Igor Loi; Antonio Pullini; Thomas Christoph Müller; Andreas Burg 001; Francesco Conti 001; Luca Benini; Philippe Flatresse (IEEE Des. Test, 2017)

A Hybrid Instruction Prefetching Mechanism for Ultra Low-Power Multicore Clusters. - Maryam Payami; Erfan Azarkhish; Igor Loi; Luca Benini (IEEE Embed. Syst. Lett., 2017)

Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster. - Davide Rossi; Antonio Pullini; Igor Loi; Michael Gautschi; Frank Kagan Gürkaynak; Adam Teman; Jeremy Constantin; Andreas Burg 001; Ivan Miro Panades; Edith Beigné; Fabien Clermidy; Philippe Flatresse; et al. (IEEE Micro, 2017)

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics. - Francesco Conti 001; Robert Schilling; Pasquale Davide Schiavone; Antonio Pullini; Davide Rossi; Frank Kagan Gürkaynak; Michael Muehlberghuber; Michael Gautschi; Igor Loi; Germain Haugou; Stefan Mangard; Luca Benini (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube. - Erfan Azarkhish; Christoph Pfister; Davide Rossi; Igor Loi; Luca Benini (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices. - Michael Gautschi; Pasquale Davide Schiavone; Andreas Traber; Igor Loi; Antonio Pullini; Davide Rossi; Eric Flamand; Frank K. Gürkaynak; Luca Benini (IEEE Trans. Very Large Scale Integr. Syst., 2017)

GAP-8: A RISC-V SoC for AI at the Edge of the IoT. - Eric Flamand; Davide Rossi; Francesco Conti 001; Igor Loi; Antonio Pullini; Florent Rotenberg; Luca Benini (ASAP, 2018)

Mr. Wolf: A 1 GFLOP/s Energy-Proportional Parallel Ultra Low Power SoC for IOT Edge Processing. - Antonio Pullini; Davide Rossi; Igor Loi; Alfio Di Mauro; Luca Benini (ESSCIRC, 2018)

Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes. - Martino Dazzi; Pierpaolo Palestri; Davide Rossi; Andrea Bandiziol; Igor Loi; David E. Bellasi; Luca Benini (ISCAS, 2018)

A Heterogeneous Multicore System on Chip for Energy Efficient Brain Inspired Computing. - Antonio Pullini; Francesco Conti 001; Davide Rossi; Igor Loi; Michael Gautschi; Luca Benini (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

The Quest for Energy-Efficient I$ Design in Ultra-Low-Power Clustered Many-Cores. - Igor Loi; Alessandro Capotondi; Davide Rossi; Andrea Marongiu; Luca Benini (IEEE Trans. Multi Scale Comput. Syst., 2018)

Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes. - Erfan Azarkhish; Davide Rossi; Igor Loi; Luca Benini (IEEE Trans. Parallel Distributed Syst., 2018)

Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing. - Antonio Pullini; Davide Rossi; Igor Loi; Giuseppe Tagliavini; Luca Benini (IEEE J. Solid State Circuits, 2019)

Energy-Efficient Two-level Instruction Cache Design for an Ultra-Low-Power Multi-core Cluster. - Jie Chen 042; Igor Loi; Luca Benini; Davide Rossi (DATE, 2020)

4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. - Davide Rossi; Francesco Conti 001; Manuel Eggimann; Stefan Mach; Alfio Di Mauro; Marco Guermandi; Giuseppe Tagliavini; Antonio Pullini; Igor Loi; Jie Chen 042; Eric Flamand; Luca Benini (ISSCC, 2021)

Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. - Davide Rossi; Francesco Conti 001; Manuel Eggimann; Alfio Di Mauro; Giuseppe Tagliavini; Stefan Mach; Marco Guermandi; Antonio Pullini; Igor Loi; Jie Chen 042; Eric Flamand; Luca Benini (CoRR, 2021)

Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. - Davide Rossi; Francesco Conti 001; Manuel Eggimann; Alfio Di Mauro; Giuseppe Tagliavini; Stefan Mach; Marco Guermandi; Antonio Pullini; Igor Loi; Jie Chen 042; Eric Flamand; Luca Benini (IEEE J. Solid State Circuits, 2022)

Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters. - Jie Chen 042; Igor Loi; Eric Flamand; Giuseppe Tagliavini; Luca Benini; Davide Rossi (CoRR, 2023)

Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters. - Jie Chen 042; Igor Loi; Eric Flamand; Giuseppe Tagliavini; Luca Benini; Davide Rossi (IEEE Trans. Very Large Scale Integr. Syst., 2023)