Machine Learning and Hardware security: Challenges and Opportunities -Invited Talk-. - Francesco Regazzoni 001; Shivam Bhasin; Amir Alipour; Ihab Alshaer; Furkan Aydin; Aydin Aysu; Vincent Beroulle; Giorgio Di Natale; Paul D. Franzon; David Hély; Naofumi Homma; Akira Ito 002; et al. (ICCAD, 2020)

Microarchitecture-aware Fault Models: Experimental Evidence and Cross-Layer Inference Methodology. - Ihab Alshaer; Brice Colombier; Christophe Deleuze; Vincent Beroulle; Paolo Maistri (DTIS, 2021)

Variable-Length Instruction Set: Feature or Bug? - Ihab Alshaer; Brice Colombier; Christophe Deleuze; Vincent Beroulle; Paolo Maistri (DSD, 2022)

Microarchitectural Insights into Unexplained Behaviors Under Clock Glitch Fault Injection. - Ihab Alshaer; Brice Colombier; Christophe Deleuze; Vincent Beroulle; Paolo Maistri (CARDIS, 2023)

Inferred Fault Models for RISC-V and Arm: A Comparative Study. - Ihab Alshaer; Ahmed Al-Kaf; Valentin Egloff; Vincent Beroulle (DFT, 2024)

Modeling Clock Glitch Fault Injection Effects on a RISC-V Microcontroller. - Ihab Alshaer; Ahmed Al-Kaf; Valentin Egloff; Vincent Beroulle (IOLTS, 2024)

Cross-layer analysis of clock glitch fault injection while fetching variable-length instructions. - Ihab Alshaer; Gijs Burghoorn; Brice Colombier; Christophe Deleuze; Vincent Beroulle; Paolo Maistri (J. Cryptogr. Eng., 2024)