A Fully Pipelined, 700MBytes/s DES Encryption Core. - Ihn Kim; Craig S. Steele; Jefferey G. Koller (Great Lakes Symposium on VLSI, 1999)

Implementation of a 32-bit RISC Processor for the Data-Intensive Architecture Processing-In-Memory Chip. - Jeffrey T. Draper; Jeff Sondeen; Sumit D. Mediratta; Ihn Kim (ASAP, 2002)

A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System. - Jeffrey T. Draper; Tim Barrett; Jeff Sondeen; Sumit D. Mediratta; Chang Woo Kang; Ihn Kim; Gokhan Daglikoca (J. VLSI Signal Process., 2005)