A 16-Kb 1T1C DRAM Supporting Conventional and Compute-in-Memory Access Modes. - Hyeonjun Cheon; Ho-Sung Lee; Jiwon Lee; Ik-Hyeon Jeon; Joo-Hyung Chae (ISOCC, 2024)

Design of 16-Kb 6T SRAM Supporting Wide Parallel Data Access for Enhanced Computation Speed. - Jiwon Lee; Hyeonjun Cheon; Ho-Sung Lee; Ik-Hyeon Jeon; Joo-Hyung Chae (ISOCC, 2024)

URcon: Unified and Reconfigurable Control and Verification Platform for Multi-Mode Customized eDRAM and SRAM Macros. - Ho-Sung Lee; Ik-Hyeon Jeon; Jiwon Lee; Hyeonjun Cheon; Joo-Hyung Chae (IEEE Access, 2025)

A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Hidden Offset-Cancellation Time and Cross-Coupled Pre-Sensing. - Ik-Hyeon Jeon; Joo-Hyung Chae (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)