Fast and accurate estimation of nano-scaled SRAM read failure probability using critical point sampling. - Ik Joon Chang; Kunhyuk Kang; Saibal Mukhopadhyay; Chris H. Kim; Kaushik Roy 001 (CICC, 2005)

Robust level converter design for sub-threshold logic. - Ik Joon Chang; Jae-Joon Kim; Kaushik Roy 001 (ISLPED, 2006)

PVT-aware leakage reduction for on-die caches with improved read stability. - Chris Hyung-Il Kim; Jae-Joon Kim; Ik-Joon Chang; Kaushik Roy 001 (IEEE J. Solid State Circuits, 2006)

A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS. - Ik Joon Chang; Jae-Joon Kim; Sang Phill Park; Kaushik Roy 001 (ISSCC, 2008)

A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors. - Ik Joon Chang; Debabrata Mohapatra; Kaushik Roy 001 (DAC, 2009)

A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS. - Ik Joon Chang; Jae-Joon Kim; Sang Phill Park; Kaushik Roy 001 (IEEE J. Solid State Circuits, 2009)

Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling. - Ik Joon Chang; Jongsun Park 001; Kunhyuk Kang; Kaushik Roy 001 (IET Circuits Devices Syst., 2010)

Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation. - Ik Joon Chang; Sang Phill Park; Kaushik Roy 001 (IEEE J. Solid State Circuits, 2010)

A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications. - Ik Joon Chang; Debabrata Mohapatra; Kaushik Roy 001 (IEEE Trans. Circuits Syst. Video Technol., 2011)

Robust Level Converter for Sub-Threshold/Super-Threshold Operation: 100 mV to 2.5 V. - Ik Joon Chang; Jae-Joon Kim; Keejong Kim; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Low-complexity frame scheduler using shared frame memory for multi-view video coding. - Minsu Choi; Jinsang Kim; Ik Joon Chang; Won-Kyung Cho (ISOCC, 2012)

A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology. - Daeyeal Lee; Ik Joon Chang; Sangyong Yoon; Joonsuc Jang; Dong-Su Jang; Wook-Ghee Hahn; Jong-Yeol Park; Doo-Gon Kim; Chiweon Yoon; Bong-Soon Lim; ByungJun Min; Sung-Won Yun; et al. (ISSCC, 2012)

Bit-error rate improvement of TLC NAND Flash using state re-ordering. - Ik Joon Chang; Joon-Sung Yang (IEICE Electron. Express, 2012)

Heterogeneous SRAM Cell Sizing for Low-Power H.264 Applications. - Jinmo Kwon; Ik Joon Chang; Insoo Lee; Heemin Park; Jongsun Park 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Low-complexity decision directed method for carrier frequency offset estimation of IEEE 802.11ad. - Junghyun Ha; Janghyuk Yoon; Ik Joon Chang; Jinsang Kim (ISCAS, 2013)

Low complexity image correction using color and focus matching for stereo video coding. - Wooseok Kim; Joohan Kim; Minsu Choi; Ik Joon Chang; Jinsang Kim (ISCAS, 2013)

Robust Buffered Clock Tree Synthesis by Sensitivity Based Link Insertion. - Joon-Sung Yang; Ik Joon Chang (IEICE Trans. Electron., 2013)

A 2-Kb One-Time Programmable Memory for UHF Passive RFID Tag IC in a Standard 0.18 µm CMOS Process. - Ngoc Dang Phan; Ik Joon Chang; Jong-Wook Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

High Performance and Hardware Efficient Multiview Video Coding Frame Scheduling Algorithms and Architectures. - Minsu Choi; Ik Joon Chang; Jinsang Kim (IEEE Trans. Circuits Syst. Video Technol., 2013)

0.2 V 8T SRAM with improved bitline sensing using column-based data randomization. - Anh-Tuan Do; Zhao Chuan Lee; Bo Wang 020; Ik-Joon Chang; Tony Tae-Hyoung Kim (A-SSCC, 2014)

a-SAD: power efficient SAD calculator for real time H.264 video encoder using MSB-approximation technique. - Trang Le Dinh Dang; Ik Joon Chang; Jinsang Kim (ISLPED, 2014)

CPAC: Energy-Efficient Data Collection through Adaptive Selection of Compression Algorithms for Sensor Networks. - HyungJune Lee; Hyunseok Kim; Ik Joon Chang (Sensors, 2014)

Low power block matching using pattern based pixel truncation. - Minsu Choi; Kyung-Rae Kim; Ik Joon Chang; Jinsang Kim (MWSCAS, 2015)

SET-Tolerant Active Body-Bias Circuits in PD-SOI CMOS Technology. - Youngkyu Jang; Ik Joon Chang; Jinsang Kim (IEICE Trans. Electron., 2015)

Variation-Aware Flip Flop for DVFS Applications. - Youngkyu Jang; Changnoh Yoon; Ik Joon Chang; Jinsang Kim (IEICE Trans. Electron., 2015)

Architecture of WLAN channel estimators. - My-Kieu Nguyen-Thi; Ik Joon Chang; Jinsang Kim (APCCAS, 2016)

An adaptive selection of an SRAM cell size for power reduction in an H.264/AVC encoder. - Hyun Kim 001; Ik Joon Chang; Hyuk-Jae Lee (ICCE, 2016)

Subthreshold 8T SRAM sizing utilizing short-channel Vt roll-off and inverse narrow-width effect. - Ik Joon Chang; Joon-Sung Yang (IEICE Electron. Express, 2016)

0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization. - Anh-Tuan Do; Zhao Chuan Lee; Bo Wang 020; Ik-Joon Chang; Xin Liu 015; Tony Tae-Hyoung Kim (IEEE J. Solid State Circuits, 2016)

Optimal reference view selection algorithm for low complexity disparity estimation. - Minsu Choi; Ik Joon Chang; Jinsang Kim (IEEE Trans. Consumer Electron., 2016)

Design of Low-Power Voltage Scalable Arithmetic Units with Perfect Timing Error Cancelation. - Ik Joon Chang; Sang Yoon Park; Jun Won Choi (Circuits Syst. Signal Process., 2017)

A 28mn FD-SOI 4KB Radiation-hardened 12T SRAM Macro with 0.6 1V Wide Dynamic Voltage Scaling for Space Applications. - Trang Le Dinh Dang; Dongkyu Seo; Jin-Woo Han; Jinsang Kim; Ik-Joon Chang (A-SSCC, 2018)

An Approximate Memory Architecture for a Reduction of Refresh Power Consumption in Deep Learning Applications. - Duy Thanh Nguyen; Hyun Kim 001; Hyuk-Jae Lee; Ik Joon Chang (ISCAS, 2018)

A Radiation Hardened SRAM with Self-refresh and Compact Error Correction. - M. Sultan M. Siddiqui; Ruchi Sharma; Van Loi Le; Taegeun Yoo; Ik-Joon Chang; Tony Tae-Hyoung Kim (ISOCC, 2018)

Optimal Selection of SRAM Bit-Cell Size for Power Reduction in Video Compression. - Hyun Kim 001; Ik Joon Chang; Hyuk-Jae Lee (IEEE J. Emerg. Sel. Topics Circuits Syst., 2018)

St-DRC: Stretchable DRAM Refresh Controller with No Parity-overhead Error Correction Scheme for Energy-efficient DNNs. - Duy Thanh Nguyen; Nhut-Minh Ho; Ik-Joon Chang (DAC, 2019)

Energy-efficient DNN-training with Stretchable DRAM Refresh Controller and Critical-bit Protection. - Duy Thanh Nguyen; Ik-Joon Chang (ISOCC, 2019)

Segmented Tag Cache: A Novel Cache Organization for Reducing Dynamic Read Energy. - Moonsoo Kim; Ik-Joon Chang; Hyuk-Jae Lee (IEEE Trans. Computers, 2019)

O-2A: Low Overhead DNN Compression with Outlier-Aware Approximation. - Nguyen-Dong Ho; Minh-Son Le; Ik-Joon Chang (DAC, 2020)

PCM: Precision-Controlled Memory System for Energy Efficient Deep Neural Network Training. - Boyeal Kim; Sang Hyun Lee; Hyun Kim 001; Duy Thanh Nguyen; Minh-Son Le; Ik Joon Chang; Dohun Kwon; Jin Hyeok Yoo; Jun Won Choi; Hyuk-Jae Lee (DATE, 2020)

DRAMA: An Approximate DRAM Architecture for High-performance and Energy-efficient Deep Training System. - Duy Thanh Nguyen; Changhong Min; Nhut-Minh Ho; Ik-Joon Chang (ICCAD, 2020)

Comparing Variation-tolerance and SEU/TID-Resilience of Three SRAM Cells in 28nm FD-SOI Technology: 6T, Quatro, and we-Quatro. - Trang Le Dinh Dang; Trinh Dinh Linh; Ngyuen Thanh Dat; Changhong Min; Jinsang Kim; Ik-Joon Chang; Jin-Woo Han (IRPS, 2020)

A Radiation-Hardened SAR ADC with Delay-Based Dual Feedback Flip-Flops for Sensor Readout Systems. - Duckhoon Ro; Changhong Min; Myounggon Kang; Ik Joon Chang; Hyung-Min Lee (Sensors, 2020)

TCL: an ANN-to-SNN Conversion with Trainable Clipping Layers. - Nguyen-Dong Ho; Ik-Joon Chang (DAC, 2021)

Posit Arithmetic for the Training and Deployment of Generative Adversarial Networks. - Nhut-Minh Ho; Duy Thanh Nguyen; Himeshi De Silva; John L. Gustafson; Weng-Fai Wong; Ik Joon Chang (DATE, 2021)

STT-MRAM Architecture with Parallel Accumulator for In-Memory Binary Neural Networks. - Thi-Nhan Pham; Kien Trinh Quang; Ik-Joon Chang; Massimo Alioto (ISCAS, 2021)

ZEM: Zero-Cycle Bit-Masking Module for Deep Learning Refresh-Less DRAM. - Duy Thanh Nguyen; Nhut-Minh Ho; Minh-Son Le; Weng-Fai Wong; Ik-Joon Chang (IEEE Access, 2021)

PR-CIM: a Variation-Aware Binary-Neural-Network Framework for Process-Resilient Computation-in-memory. - Minh-Son Le; Thi-Nhan Pham; Thanh-Dat Nguyen; Ik-Joon Chang (CoRR, 2021)

OBET: On-the-Fly Byte-Level Error Tracking for Correcting and Detecting Faults in Unreliable DRAM Systems. - Duy Thanh Nguyen; Nhut-Minh Ho; Weng-Fai Wong; Ik-Joon Chang (Sensors, 2021)

A 133.6TOPS/W Compute-In-Memory SRAM Macro with Fully Parallel One-Step Multi-Bit Computation. - Edward Jongyoon Choi; Injun Choi; Chanhee Jeon; Gichan Yun; Donghyeon Yi; Sohmyung Ha; Ik-Joon Chang; Minkyu Je (CICC, 2022)

An SRAM-Based Hybrid Computation-in-Memory Macro Using Current-Reused Differential CCO. - Injun Choi; Edward Jongyoon Choi; Donghyeon Yi; Yoontae Jung; Hoyong Seong; Hyuntak Jeon; Soon-Jae Kweon; Ik-Joon Chang; Sohmyung Ha; Minkyu Je (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

STT-BNN: A Novel STT-MRAM In-Memory Computing Macro for Binary Neural Networks. - Thi-Nhan Pham; Quang-Kien Trinh; Ik-Joon Chang; Massimo Alioto (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

TRIO: a Novel 10T Ternary SRAM Cell for Area-Efficient In-memory Computing of Ternary Neural Networks. - Thanh-Dat Nguyen; Minh-Son Le; Thi-Nhan Pham; Ik-Joon Chang (AICAS, 2023)

A 333TOPS/W Logic-Compatible Multi-Level Embedded Flash Compute-In-Memory Macro with Dual-Slope Computation. - Edward Jongyoon Choi; Injun Choi; Vincent Lukito; Dong-Hwi Choi; Donghyeon Yi; Ik-Joon Chang; Sohmyung Ha; Minkyu Je (CICC, 2023)

Transistor Sizing Scheme for DICE-Based Radiation-Resilient Latches. - Jung-Jin Park; Young-Min Kang; Geon-Hak Kim; Ik-Joon Chang; Jinsang Kim (ICEIC, 2023)

O-2A: Outlier-Aware Compression for 8-bit Post-Training Quantization Model. - Nguyen-Dong Ho; Ik-Joon Chang (IEEE Access, 2023)

Low-Complexity Double-Node-Upset Resilient Latch Design Using Novel Stacked Cross-Coupled Elements. - Young-Min Kang; Jung-Jin Park; Geon-Hak Kim; Ik-Joon Chang; Jinsang Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

MiCE: An ANN-to-SNN Conversion Technique to Enable High Accuracy and Low Latency. - Nguyen-Dong Ho; Ik-Joon Chang (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

A 639.38GOPS Hybrid-Domain Logic-Compatible Multi-Level Embedded Flash Computing-in-Memory Macro with Spike-Edge Computation. - Jiho Chun; Edward Jongyoon Choi; Byeongseon Choi; Donghyeon Yi; Sohmyung Ha; Ik-Joon Chang; Minkyu Je (A-SSCC, 2024)

MERSIT: A Hardware-Efficient 8-bit Data Format with Enhanced Post-Training Quantization DNN Accuracy. - Nguyen-Dong Ho; Gyujun Jeong; Cheol-Min Kang; Seungkyu Choi; Ik-Joon Chang (DAC, 2024)

An SRAM-based Error-Free Time Domain Pulse Train Computing-In-Memory Macro achieving 226.14 TOPS/W and 5.782 TOPS/mm2. - Edward Jongyoon Choi; Jiho Chun; Byeongseon Choi; Sohmyung Ha; Ik-Joon Chang; Minkyu Je (ISOCC, 2024)

A Δ-Based Spike Sorting SoC with End-to-End Implementation of Event-Driven Binary Autoencoder Neural Network in Analog CIM Achieving 94.54% Accuracy and 3.11μW/ch. - Edward Jongyoon Choi; Vincent Lukito; Injun Choi; Seoyoung Lee; Ik-Joon Chang; Sohmyung Ha; Minkyu Je (VLSI Technology and Circuits, 2024)

TRIO-TCAM: An Area and Energy-Efficient Triple-State-in-Cell Ternary Content-Addressable Memory Architecture. - Thanh-Dat Nguyen; Sungju Ryu; Ik-Joon Chang (IEEE Access, 2024)

FLARE: FP-Less PTQ and Low-ENOB ADC Based AMS-PiM for Error-Resilient, Fast, and Efficient Transformer Acceleration. - Donghyeon Yi; Seoyoung Lee; Jongho Kim; Junyoung Kim; Sohmyung Ha; Ik Joon Chang; Minkyu Je (CoRR, 2024)

Skew-CIM: Process-Variation-Resilient and Energy-Efficient Computation-in-Memory Design Technique With Skewed Weights. - Donghyeon Yi; Seoyoung Lee; Injun Choi; Gichan Yun; Edward Jongyoon Choi; Jonghee Park; Jonghoon Kwak; Sung-Joon Jang; Sohmyung Ha; Ik-Joon Chang; Minkyu Je (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

STT-HDC: An Efficient Time-Domain In-Memory Hyper-Dimensional Computing Design Based on STT-MRAM. - Thi-Nhan Pham; Quang-Kien Trinh; Thanh-Dat Nguyen; Ik-Joon Chang (IEEE Access, 2025)

Qrazor: Reliable and effortless 4-bit llm quantization by significant data razoring. - Dongyoung Lee; Seungkyu Choi; Ik Joon Chang (CoRR, 2025)