Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices. - Seongjae Cho; Jang-Gn Yun; Il-Han Park; Jung Hoon Lee; Jong Pil Kim; Jong Duk Lee; Hyungcheol Shin; Byung-Gook Park (IEICE Trans. Electron., 2007)

Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI). - Seongjae Cho; Il-Han Park; Jung Hoon Lee; Jang-Gn Yun; Doo-Hyun Kim; Jong Duk Lee; Hyungcheol Shin; Byung-Gook Park (IEICE Trans. Electron., 2008)

Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme. - Jang-Gn Yun; Il-Han Park; Seongjae Cho; Jung Hoon Lee; Doo-Hyun Kim; Gil Sung Lee; Yoon Kim; Jong Duk Lee; Byung-Gook Park (IEICE Trans. Electron., 2008)

3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array. - Yoon Kim; Seongjae Cho; Gil Sung Lee; Il-Han Park; Jong Duk Lee; Hyungcheol Shin; Byung-Gook Park (IEICE Trans. Electron., 2009)

Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory. - Doo-Hyun Kim; Il-Han Park; Seongjae Cho; Jong Duk Lee; Hyungcheol Shin; Byung-Gook Park (IEICE Trans. Electron., 2009)

A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology. - Daeyeal Lee; Ik Joon Chang; Sangyong Yoon; Joonsuc Jang; Dong-Su Jang; Wook-Ghee Hahn; Jong-Yeol Park; Doo-Gon Kim; Chiweon Yoon; Bong-Soon Lim; ByungJun Min; Sung-Won Yun; et al. (ISSCC, 2012)

Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH. - Yong-Sung Cho; Il-Han Park; Sangyong Yoon; Nam-Hee Lee; Sang-Hyun Joo; Ki-Whan Song; Kihwan Choi; Jin-Man Han; Kyehyun Kyung; Young-Hyun Jun (IEEE J. Solid State Circuits, 2013)

7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate. - Seungjae Lee 001; Jin-Yub Lee; Il-Han Park; Jong-Yeol Park; Sung-Won Yun; Minsu Kim 004; Jong-Hoon Lee; Min-Seok Kim; Kangbin Lee; Taeeun Kim; Byungkyu Cho; Dooho Cho; et al. (ISSCC, 2016)

11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory. - Chulbum Kim; Ji-Ho Cho; Woopyo Jeong; Il-Han Park; Hyun Wook Park; Doo-Hyun Kim; Daewoon Kang; Sunghoon Lee; Ji-Sang Lee; Wontae Kim 004; Jiyoon Park; Yang-Lo Ahn; et al. (ISSCC, 2017)

A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory. - Chulbum Kim; Doo-Hyun Kim; Woopyo Jeong; Hyun-Jin Kim; Il-Han Park; Hyun Wook Park; Jong-Hoon Lee; Jiyoon Park; Yang-Lo Ahn; Ji Young Lee; Seungbum Kim; Hyun-Jun Yoon; et al. (IEEE J. Solid State Circuits, 2018)

Machine-Learning-Based Read Reference Voltage Estimation for NAND Flash Memory Systems Without Knowledge of Retention Time. - Hyemin Choe; Jeongju Jee; Seung-Chan Lim; Sung-Min Joe; Il-Han Park; Hyuncheol Park (IEEE Access, 2020)

High Bit Cost Scalability and Reliable Cell Characteristics for 7th Generation 1Tb 4Bit/Cell 3D-NAND Flash. - Kyungmoon Kim; Yujeong Seo; Sejun Park; Woojae Jang; Dongho Yoo; Joonsung Lim; Il-Han Park; Jaeduk Lee; Kyungyoon Noh; Sujin Ahn; Sunghoi Hur (VLSI Technology and Circuits, 2023)

Magnetic Field Analysis of Electric Current in Coplanar Coils Using Equivalent Permanent Magnetization and Magnetic Scalar Potential. - Jong Oh Park; Jun Seong Lee; Il-Han Park (IEEE Access, 2024)