26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS. - Ba-Ro-Saim Sung; Dong-Shin Jo; Il-Hoon Jang; Dong-Suk Lee; Yong-Sang You; Yong-Hee Lee; Ho-Jin Park; Seung-Tak Ryu (ISSCC, 2015)

An incremental zoom sturdy MASH ADC. - Ki-Hoon Seo; Il-Hoon Jang; Kyung-Jun Noh; Seung-Tak Ryu (MWSCAS, 2017)

A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling. - Il-Hoon Jang; Min-Jae Seo; Sang-Hyun Cho; Jae-Keun Lee; Seung-Yeob Baek 002; Sunwoo Kwon; Michael Choi; Hyungjong Ko; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2018)

A 12b 600MS/s Pipelined SAR and 2x-Interleaved Incremental Delta-Sigma ADC with Source-Follower-Based Residue-Transfer Scheme in 7nm FinFET. - Seung-Yeob Baek 002; Il-Hoon Jang; Michael Choi; Hyungdong Roh; Woongtaek Lim; Youngjae Cho; Jongshin Shin (ISSCC, 2021)

A 4th-Order Continuous-Time Delta-Sigma Modulator With Hybrid Noise-Coupling. - Kent Edrian Lozada; Il-Hoon Jang; Gyeom-Je Bae; Dong-Hun Lee; Ye-Dam Kim; Hankyu Lee; Seong Joong Kim; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Continuous-Time Delta-Sigma Modulator with SAR-Assisted Digital Noise Coupling. - Kent Edrian Lozada; Il-Hoon Jang; Ye-Dam Kim; Seung-Tak Ryu (CICC, 2025)