An on-chip TSV emulation using metal bar surrounded by metal ring to develop interface circuits. - Il-Min Yi; Seung-Jun Bae; Young-Soo Sohn; Jae-Yoon Sim; Hong-June Park (ISOCC, 2012)

A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines. - Hae-Kang Jung; Il-Min Yi; Soo-Min Lee; Jae-Yoon Sim; Hong-June Park (IEEE J. Solid State Circuits, 2012)

An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface. - Soo-Min Lee; Il-Min Yi; Hae-Kang Jung; Hyunbae Lee; Yong-Ju Kim; Yunsaing Kim; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE J. Solid State Circuits, 2014)

A 40-mV-Swing Single-Ended Transceiver for TSV with a Switched-Diode RX Termination. - Il-Min Yi; Soo-Min Lee; Seung-Jun Bae; Young-Soo Sohn; Jung-Hwan Choi; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme. - Il-Min Yi; Seung-Jun Bae; Min-Kyun Chae; Soo-Min Lee; Young Jae Jang; Young-Chul Cho; Young-Soo Sohn; Jung-Hwan Choi; Seong-Jin Jang; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (VLSI Circuits, 2016)

A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface. - Soo-Min Lee; Ji-Hoon Lim; Il-Min Yi; Young Jae Jang; Hae-Kang Jung; Kyunghoon Kim; Dae-Han Kwon; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE J. Solid State Circuits, 2016)

A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s. - Il-Min Yi; Soo-Min Lee; Seung-Jun Bae; Young-Soo Sohn; Jung-Hwan Choi; Seong-Jin Jang; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

23.7 A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS. - Il-Min Yi; Min-Kyun Chae; Seok-Hun Hyun; Seung-Jun Bae; Jung-Hwan Choi; Seong-Jin Jang; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (ISSCC, 2017)

A 15.1-mW 6-GS/s 6-bit Flash ADC with Selectively Activated 8× Time-Domain Interpolation. - Il-Min Yi; Naoki Miura; Hiroyuki Fukuyama; Hideyuki Nosaka (A-SSCC, 2018)

A Summer-Embedded Sense Amplifier for High-Speed Decision Feedback Equalizer. - Il-Min Yi; Naoki Miura; Hiroyuki Fukuyama; Hideyuki Nosaka (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface. - Il-Min Yi; Min-Kyun Chae; Seok-Hun Hyun; Seung-Jun Bae; Jung-Hwan Choi; Seong-Jin Jang; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE J. Solid State Circuits, 2018)

A 15.1-mW 6-GS/s 6-bit Single-Channel Flash ADC With Selectively Activated 8× Time-Domain Latch Interpolation. - Il-Min Yi; Naoki Miura; Hiroyuki Fukuyama; Hideyuki Nosaka (IEEE J. Solid State Circuits, 2021)

A 4-GS/s 11.3-mW 7-bit Time-Based ADC With Folding Voltage-to-Time Converter and Pipelined TDC in 65-nm CMOS. - Il-Min Yi; Naoki Miura; Hideyuki Nosaka (IEEE J. Solid State Circuits, 2021)

A Jitter-Robust 40Gb/s ADC-Based Multicarrier Receiver Front End in 22nm FinFET. - Yuanming Zhu; Julian Camilo Gomez Diaz; Srujan Kumar Kaile; Il-Min Yi; Tong Liu; Sebastian Hoyos; Samuel Palermo (CICC, 2022)

A 38GS/s 7b Time-Interleaved Pipelined-SAR ADC with Speed-Enhanced Bootstrapped Switch in 22nm FinFET. - Yuanming Zhu; Tong Liu; Srujan Kumar Kaile; Shiva Kiran; Il-Min Yi; Ruida Liu; Julian Camilo Gomez Diaz; Sebastian Hoyos; Samuel Palermo (CICC, 2022)

LLM: Realizing Low-Latency Memory by Exploiting Embedded Silicon Photonics for Irregular Workloads. - Marjan Fariborz; Mahyar Samani; Pouya Fotouhi; Roberto Proietti; Il-Min Yi; Venkatesh Akella; Jason Lowe-Power; Samuel Palermo; S. J. Ben Yoo (ISC, 2022)

A Direct Bond Interconnect 3D Co-Integrated Silicon-Photonic Transceiver in 12nm FinFET with -20.3dBm OMA Sensitivity and 691fJ/bit. - Anirban Samanta; Po-Hsuan Chang; Peng Yan; Mingye Fu; Mehmet Berkay On; Ankur Kumar; Hyungryul Kang; Il-Min Yi; Dedeepya Annabattuni; Yu Zhang 099; David Scott; Robert Patti; et al. (OFC, 2023)

A Sub-500fJ/bit 3D Direct Bond Silicon Photonic Transceiver in 12nm FinFET. - Po-Hsuan Chang; Anirban Samanta; Peng Yan; Mingye Fu; Yu Zhang 099; Mehmet Berkay On; Ankur Kumar; Hyungryul Kang; Il-Min Yi; Dedeepya Annabattuni; David Scott; Robert Patti; et al. (VLSI Technology and Circuits, 2023)

A 50Gb/s DAC-Based Multicarrier Polar Transmitter in 22nm FinFET. - Il-Min Yi; Srujan Kumar Kaile; Yuanming Zhu; Julian Camilo Gomez Diaz; Sebastian Hoyos; Samuel Palermo (VLSI Technology and Circuits, 2023)

A 38-GS/s 7-bit Pipelined-SAR ADC With Speed- Enhanced Bootstrapped Switch and Output Level Shifting Technique in 22-nm FinFET. - Yuanming Zhu; Tong Liu; Srujan Kumar Kaile; Shiva Kiran; Il-Min Yi; Ruida Liu; Julian Camilo Gomez Diaz; Sebastian Hoyos; Samuel Palermo (IEEE J. Solid State Circuits, 2023)

A Jitter-Robust 40 Gb/s ADC-Based Multicarrier Receiver Front-End With 4-GS/s Baseband Pipeline-SAR ADCs in 22-nm FinFET. - Yuanming Zhu; Julian Camilo Gomez Diaz; Srujan Kumar Kaile; Il-Min Yi; Tong Liu; Sebastian Hoyos; Samuel Palermo (IEEE J. Solid State Circuits, 2023)

Comparisons of Metastability Impact in Time-Domain and Asynchronous SAR ADCs for Serial I/O Receivers. - Gijin Park; Srujan Kumar Kaile; Il-Min Yi; Sebastian Hoyos; Samuel Palermo (MWSCAS, 2024)

A 42.7Gb/s Optical Receiver With Digital Clock and Data Recovery in 28nm CMOS. - Hyungryul Kang; Inhyun Kim; Ruida Liu; Ankur Kumar; Il-Min Yi; Yuan Yuan 033; Zhihong Huang; Samuel Palermo (IEEE Access, 2024)

A 50-Gb/s Multicarrier Transmitter Using DAC-Based Polar Drivers in 22-nm FinFET. - Il-Min Yi; Srujan Kumar Kaile; Yuanming Zhu; Julian Camilo Gomez Diaz; Sebastian Hoyos; Samuel Palermo (IEEE J. Solid State Circuits, 2024)