Multiplex: unifying conventional and speculative thread-level parallelism on a chip multiprocessor. - Chong-liang Ooi; Seon Wook Kim; Il Park 001; Rudolf Eigenmann; Babak Falsafi; T. N. Vijaykumar (ICS, 2001)

Reducing register ports for higher speed and lower energy. - Il Park 001; Michael D. Powell; T. N. Vijaykumar (MICRO, 2002)

Iimplicitly-Multithreaded Processors. - Il Park 001; Babak Falsafi; T. N. Vijaykumar (ISCA, 2003)

Reducing Design Complexity of the Load/Store Queue. - Il Park 001; Chong-liang Ooi; T. N. Vijaykumar (MICRO, 2003)

Do Trace Cache, Value Prediction and Prefetching Improve SMT Throughput?. - Chen-Yong Cher; Il Park 001; T. N. Vijaykumar (ARCS, 2006)

Content-Aware Bit Shuffling for Maximizing PCM Endurance. - Miseon Han; Youngsun Han; Seon Wook Kim; Hokyoon Lee; Il Park 001 (ACM Trans. Design Autom. Electr. Syst., 2017)

A 512GB 1.1V Managed DRAM Solution with 16GB ODP and Media Controller. - Seong Ju Lee; Byung Deuk Jeon; Kyeong Pil Kang; Dong Yoon Ka; Na Yeon Kim; Yongseop Kim; Yunseok Hong; Mankeun Kang; Jinyong Min; Mingyu Lee; Chunseok Jeong; Kwandong Kim; et al. (ISSCC, 2019)

Design of Processing-"Inside"-Memory Optimized for DRAM Behaviors. - Won Jun Lee; Chang Hyun Kim; Yoonah Paik; Jongsun Park 001; Il Park 001; Seon Wook Kim (IEEE Access, 2019)

Newton: A DRAM-maker's Accelerator-in-Memory (AiM) Architecture for Machine Learning. - Mingxuan He; Choungki Song; Ilkon Kim; Chunseok Jeong; Seho Kim; Il Park 001; Mithuna Thottethodi; T. N. Vijaykumar (MICRO, 2020)

System Architecture and Software Stack for GDDR6-AiM. - Yongkee Kwon; Kornijcuk Vladimir; Nahsung Kim; Woojae Shin; Jongsoon Won; Minkyu Lee; Hyunha Joo; Haerang Choi; Guhyun Kim; Byeongju An; Jeongbin Kim 001; Jaewook Lee; et al. (HCS, 2022)

Holistic approaches to memory solutions for the Autonomous Driving Era. - Daeyong Shim; Chunseok Jeong; Euncheol Lee; Junmo Kang; Seokcheol Yoon; Yongkee Kwon; Il Park 001; Hyun Ahn; Seonyong Cha; Jinkook Kim (ISCAS, 2022)

A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications. - Seong Ju Lee; Kyu-Young Kim; Sanghoon Oh; Joonhong Park; Gimoon Hong; Dong Yoon Ka; Kyu-Dong Hwang; Jeongje Park; Kyeong Pil Kang; Jungyeon Kim; Junyeol Jeon; Nahsung Kim; et al. (ISSCC, 2022)

Silent-PIM: Realizing the Processing-in-Memory Computing With Standard Memory Requests. - Chang Hyun Kim; Won Jun Lee; Yoonah Paik; Kiyong Kwon; Seok Young Kim; Il Park 001; Seon Wook Kim (IEEE Trans. Parallel Distributed Syst., 2022)

Low-overhead inverted LUT design for bounded DNN activation functions on floating-point vector ALUs. - Seok Young Kim; Chang Hyun Kim; Won Joon Lee; Il Park 001; Seon Wook Kim (Microprocess. Microsystems, 2022)

A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application. - Dae-Han Kwon; Seongju Lee; Kyuyoung Kim; Sanghoon Oh; Joonhong Park; Gimoon Hong; Dongyoon Ka; Kyu-Dong Hwang; Jeongje Park; Kyeong Pil Kang; Jungyeon Kim; Junyeol Jeon; et al. (IEEE J. Solid State Circuits, 2023)