Power Analysis Resilient SRAM Design Implemented with a 1% Area Overhead Impedance Randomization Unit for Security Applications. - Robert Giterman; Maoz Wicentowski; Oron Chertkow; Ilan Sever; Ishai Kehati; Yoav Weizman; Osnat Keren; Alexander Fish (ESSCIRC, 2019)

Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads. - Yoav Weizman; Robert Giterman; Oron Chertkow; Maoz Wicentowski; Itamar Levi; Ilan Sever; Ishai Kehati; Osnat Keren; Alexander Fish (IEEE Access, 2021)

Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro. - Bastien Giraud; Sebastien Ricavy; Yasser Moursy; Cyrille Laffond; Ilan Sever; Valentin Gherman; Manuel Pezzin; Florent Lepin; Mariam Diallo; Khadija Zenati; Sylvain Dumas; Maxim Vershkov; et al. (IMW, 2023)

Smart Write Algorithm to Enhance Performances and Reliability of an RRAM Macro. - Bastien Giraud; Sebastien Ricavy; Cyrille Laffond; Ilan Sever; Valentin Gherman; Florent Lepin; Mariam Diallo; Khadija Zenati; Sylvain Dumas; Olivier Guille; Maxim Vershkov; Alessandro Bricalli; et al. (IEEE J. Solid State Circuits, 2024)