Off-state degradation with ac bias in PMOSFET. - Segeun Park; Hyuckchai Jung; Jeonghoon Oh; Ilgweon Kim; Hyoungsun Hong; Gyoyoung Jin; Yonghan Roh (Microelectron. Reliab., 2016)

A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process. - Jin-Hyeok Baek; Chang-Kyo Lee; Kiho Kim; Daesik Moon; Gil-Hoon Cha; Jin-Seok Heo; Min-Su Ahn; Dong-Ju Kim; Jae-Joon Song; Seokhong Kwon; Jongmin Kim; Kyung-Soo Kim; et al. (VLSI Circuits, 2018)

Effect of Back Gate on Word Line Disturb Immunity of a Vertical Channel DRAM Cell Array Transistor. - Moonyoung Jeong; Sangho Lee; Yootak Jun; Kiseok Lee; Seokhan Park; Jeonghoon Oh; Ilgweon Kim; Jemin Park (IRPS, 2024)

A Metal Dual Work-Function Gate (MDWG) for the Continuous Scaling of DRAM Cell Transistors. - Junsoo Kim; Hyun Jung Lee; Sung Ho Jang; Jun Bum Lee; Ilgweon Kim; Jeonghoon Oh; Jemin Park; Jaihyuk Song (VLSI Technology and Circuits, 2024)