Realization of a programmable rank-order filter architecture using capacitive threshold logic gates. - Ilhan Hatirnaz; Frank K. Gürkaynak; Yusuf Leblebici (ISCAS (1), 1999)

A compact modular architecture for high-speed binary sorting. - Ilhan Hatirnaz; Frank K. Gürkaynak; Yusuf Leblebici (ICASSP, 2000)

A compact modular architecture for the realization of high-speed binary sorting engines based on rank ordering. - Ilhan Hatirnaz; Frank K. Gürkaynak; Yusuf Leblebici (ISCAS, 2000)

A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic. - Ilhan Hatirnaz; Frank K. Gürkaynak; Yusuf Leblebici (VLSI Design, 2000)

Full-custom CMOS realization of a high-performance binary sorting engine with linear area-time complexity. - Turan Demirci; Ilhan Hatirnaz; Yusuf Leblebici (ISCAS (5), 2003)

Twisted differential on-chip interconnect architecture for inductive/capacitive crosstalk noise cancellation. - Ilhan Hatirnaz; Yusuf Leblebici (SoC, 2003)

Modelling and implementation of twisted differential on-chip interconnects for crosstalk noise reduction. - Ilhan Hatirnaz; Yusuf Leblebici (ISCAS (5), 2004)

Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design. - Elizabeth J. Brauer; Ilhan Hatirnaz; Stéphane Badel; Yusuf Leblebici (ISCAS, 2006)

Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells. - Stéphane Badel; Ilhan Hatirnaz; Yusuf Leblebici; Elizabeth J. Brauer (VLSI-SoC, 2006)

Early wire characterization for predictable network-on-chip global interconnects. - Ilhan Hatirnaz; Stéphane Badel; Nuria Pazos; Yusuf Leblebici; Srinivasan Murali; David Atienza; Giovanni De Micheli (SLIP, 2007)