Towards a Comprehensive SET Analysis Flow for VLSI Circuits using Static Timing Analysis. - Christos Georgakidis; Dimitris Valiantzas; Stavros Simoglou; Iordanis Lilitsis; Nikolaos Chatzivangelis; Ilias Golfos; Marko S. Andjelkovic; Christos P. Sotiriou; Milos Krstic (DFT, 2023)