Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints. - Ana Azevedo; Ilya Issenin; Radu Cornea; Rajesh Gupta 001; Nikil D. Dutt; Alexander V. Veidenbaum; Alexandru Nicolau (DATE, 2002)

Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies. - Ilya Issenin; Erik Brockmeyer; Miguel Miranda; Nikil D. Dutt (DATE, 2004)

Compilation techniques for energy reduction in horizontally partitioned cache architectures. - Aviral Shrivastava; Ilya Issenin; Nikil D. Dutt (CASES, 2005)

FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations. - Ilya Issenin; Nikil D. Dutt (DATE, 2005)

Mitigating soft error failures for multimedia applications by selective data protection. - Kyoungwoo Lee; Aviral Shrivastava; Ilya Issenin; Nikil D. Dutt; Nalini Venkatasubramanian (CASES, 2006)

Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications. - Ilya Issenin; Nikil D. Dutt (CODES+ISSS, 2006)

Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies. - Ilya Issenin; Erik Brockmeyer; Bart Durinck; Nikil D. Dutt (DAC, 2006)

Software controlled memory layout reorganization for irregular array access patterns. - Doosan Cho; Ilya Issenin; Nikil D. Dutt; Jonghee W. Yoon; Yunheung Paek (CASES, 2007)

Data Reuse Driven Memory and Network-On-Chip Co-Synthesis. - Ilya Issenin; Nikil D. Dutt (IESS, 2007)

DRDU: A data reuse analysis technique for efficient scratch-pad memory management. - Ilya Issenin; Erik Brockmeyer; Miguel Miranda; Nikil D. Dutt (ACM Trans. Design Autom. Electr. Syst., 2007)

A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures. - Aviral Shrivastava; Ilya Issenin; Nikil D. Dutt (ASP-DAC, 2008)

Compiler driven data layout optimization for regular/irregular array access patterns. - Doosan Cho; Sudeep Pasricha; Ilya Issenin; Nikil D. Dutt; Yunheung Paek; SunJun Ko (LCTES, 2008)

Using FORAY Models to Enable MPSoC Memory Optimizations. - Ilya Issenin; Nikil D. Dutt (Int. J. Parallel Program., 2008)

Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications. - Ilya Issenin; Erik Brockmeyer; Bart Durinck; Nikil D. Dutt (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications. - Doosan Cho; Sudeep Pasricha; Ilya Issenin; Nikil D. Dutt; Minwook Ahn; Yunheung Paek (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures. - Aviral Shrivastava; Ilya Issenin; Nikil D. Dutt; Sanghyun Park; Yunheung Paek (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Partially Protected Caches to Reduce Failures Due to Soft Errors in Multimedia Applications. - Kyoungwoo Lee; Aviral Shrivastava; Ilya Issenin; Nikil D. Dutt; Nalini Venkatasubramanian (IEEE Trans. Very Large Scale Integr. Syst., 2009)