Speeding-Up Simulation-Based Fault Injection of Complex HDL Models. - Ilya Tuzov; Juan Carlos Ruiz 001; David de Andrés; Pedro J. Gil (LADC, 2016)

Dependability-Aware Design Space Exploration for Optimal Synthesis Parameters Tuning. - Ilya Tuzov; David de Andrés; Juan Carlos Ruiz 001 (DSN, 2017)

Accurately Simulating the Effects of Faults in VHDL Models Described at the Implementation-Level. - Ilya Tuzov; Juan Carlos Ruiz 001; David de Andrés (EDCC, 2017)

DAVOS: EDA Toolkit for Dependability Assessment, Verification, Optimisation and Selection of Hardware Models. - Ilya Tuzov; David de Andrés; Juan Carlos Ruiz 001 (DSN, 2018)

Accurate Robustness Assessment of HDL Models Through Iterative Statistical Fault Injection. - Ilya Tuzov; David de Andrés; Juan Carlos Ruiz 001 (EDCC, 2018)

Speeding-Up Robustness Assessment of HDL Models through Profiling and Multi-Level Fault Injection. - Ilya Tuzov; David de Andrés; Juan Carlos Ruiz 001 (LADC, 2018)

Tuning synthesis flags to optimize implementation goals: Performance and robustness of the LEON3 processor as a case study. - Ilya Tuzov; David de Andrés; Juan Carlos Ruiz 001 (J. Parallel Distributed Comput., 2018)

Robustness-Aware Design Space Exploration Through Iterative Refinement of D-Optimal Designs. - Ilya Tuzov; David de Andrés; Juan Carlos Ruiz 001 (EDCC, 2019)

Simulating the effects of logic faults in implementation-level VITAL-compliant models. - Ilya Tuzov; David de Andrés; Juan Carlos Ruiz 001 (Computing, 2019)

Improving Robustness-Aware Design Space Exploration for FPGA-Based Systems. - Ilya Tuzov; David de Andrés; Juan Carlos Ruiz 001 (EDCC, 2020)

Improving the Robustness of Redundant Execution with Register File Randomization. - Ilya Tuzov; Pablo Andreu; Laura Medina; Tomás Picornell; Antonio Robles; Pedro López 001; José Flich; Carles Hernández 001 (ICCAD, 2021)

Using Look Up Table Content as Signatures to Identify IP Cores in Modern FPGAs. - Ali Asghar; Amanda Katherine Robillard; Ilya Tuzov; Andreas Becher; Daniel Ziener (ARCS, 2022)

Reversing FPGA architectures for speeding up fault injection: does it pay? - Ilya Tuzov; David de Andrés; Juan Carlos Ruiz 001 (EDCC, 2022)

BAFFI: a bit-accurate fault injector for improved dependability assessment of FPGA prototypes. - Ilya Tuzov; David de Andrés; Juan-Carlos Ruiz-Garcia 001; Carles Hernández 001 (DATE, 2023)

A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors. - Jens Anders; Pablo Andreu; Bernd Becker 001; Steffen Becker 001; Riccardo Cantoro; Nikolaos Ioannis Deligiannis; Nourhan Elhamawy; Tobias Faller; Carles Hernández 001; Nele Mentens; Mahnaz Namazi Rizi; Ilia Polian; et al. (ETS, 2023)