Imran Hafeez Abbassi

Orcid: 0000-0002-3950-6725

According to our database1, Imran Hafeez Abbassi authored at least 8 papers between 2016 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2022
ForASec: Formal Analysis of Hardware Trojan-Based Security Vulnerabilities in Sequential Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2019
Using gate-level side channel parameters for formally analyzing vulnerabilities in integrated circuits.
Sci. Comput. Program., 2019

TrojanZero: Switching Activity-Aware Design of Undetectable Hardware Trojans with Zero Power and Area Footprint.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
ForASec: Formal Analysis of Security Vulnerabilities in Sequential Circuits.
CoRR, 2018

McSeVIC: A Model Checking Based Framework for Security Vulnerability Analysis of Integrated Circuits.
IEEE Access, 2018

Accelerating Viterbi Algorithm using Custom Instruction Approach.
Proceedings of the 14th IEEE/ASME International Conference on Mechatronic and Embedded Systems and Applications, 2018

2016
A self-learning framework to detect the intruded integrated circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Formal Verification of Gate-Level Multiple Side Channel Parameters to Detect Hardware Trojans.
Proceedings of the Formal Techniques for Safety-Critical Systems, 2016


  Loading...