Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults. - Imran Wali; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Aida Todri (DDECS, 2014)

An effective hybrid fault-tolerant architecture for pipelined cores. - Imran Wali; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001 (ETS, 2015)

Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture. - Imran Wali; Arnaud Virazel; Alberto Bosio; Patrick Girard 001; Matteo Sonza Reorda (IOLTS, 2015)

A low-cost susceptibility analysis methodology to selectively harden logic circuits. - Imran Wali; Bastien Deveautour; Arnaud Virazel; Alberto Bosio; Patrick Girard 001; Matteo Sonza Reorda (ETS, 2016)

A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores. - Imran Wali; Arnaud Virazel; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Matteo Sonza Reorda (J. Electron. Test., 2016)

An efficient framework for design and assessment of arithmetic operators with Reduced-Precision Redundancy. - Imran Wali; Emmanuel Casseau; Arnaud Tisserand (DASIP, 2017)

Towards approximation during test of Integrated Circuits. - Imran Wali; Marcello Traiola; Arnaud Virazel; Patrick Girard 001; Mario Barbareschi; Alberto Bosio (DDECS, 2017)

A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits. - Imran Wali; Bastien Deveautour; Arnaud Virazel; Alberto Bosio; Patrick Girard 001; Matteo Sonza Reorda (J. Electron. Test., 2017)

Analyzing the impact of the Operating System on the Reliability of a RISC-V FPGA Implementation. - Imran Wali; Alfonso Sánchez-Macián; Alexis Ramos; Juan Antonio Maestro (ICECS, 2020)