A graph approach to DFT hardware placement for robust delay fault BIST. - Imtiaz P. Shaik; Michael L. Bushnell (VLSI Design, 1995)

Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming . - Imtiaz P. Shaik; Michael L. Bushnell (VTS, 1995)

Testability Features of AMD-K6TM Microprocessor. - R. Scott Fetherston; Imtiaz P. Shaik; Siyad C. Ma (ITC, 1997)

Testability Features of the AMD-K6 Microprocessor. - R. Scott Fetherston; Imtiaz P. Shaik; Siyad C. Ma (IEEE Des. Test Comput., 1998)

A comparison of bridging fault simulation methods. - R. Scott Fetherston; Imtiaz P. Shaik; Siyad C. Ma (ITC, 1999)