An O(n3logn)-Heuristic for Microcode Bit Optimization. - Se-Kyoung Hong; In-Cheol Park; Chong-Min Kyung (ICCAD, 1990)

Fast and Near Optimal Scheduling in Automatic Data Path Aynthesis. - In-Cheol Park; Chong-Min Kyung (DAC, 1991)

FAMOS: an efficient scheduling algorithm for high-level synthesis. - In-Cheol Park; Chong-Min Kyung (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Two Complementary Approaches for Microcode Bit Optimization. - In-Cheol Park; Se-Kyoung Hong; Chong-Min Kyung (IEEE Trans. Computers, 1994)

HK386: an x86-compatible 32-bit CISC microprocessor. - Chong-Min Kyung; In-Cheol Park; Se-Kyoung Hong; K. S. Seong; B. S. Kong; Seungjong Lee; Hoon Choi; S. R. Maeng; D. T. Kim; Jong-Sun Kim; S. H. Park; Y. J. Kang (ASP-DAC, 1997)

Multi-project chip activities in Korea-IDEC perspective. - Chong-Min Kyung; In-Cheol Park; Ho-Jun Song (ASP-DAC, 1997)

Single cycle access cache for the misaligned data and instruction prefetch. - Joon-Seo Yim; Hee-Choul Lee; Tae-Hoon Kim; Bong-Il Park; Chang-Jae Park; In-Cheol Park; Chong-Min Kyung (ASP-DAC, 1997)

Verification methodology of compatible microprocessors. - Joon-Seo Yim; Chang-Jae Park; Woo-Seung Yang; Hun-Seung Oh; Hee-Choul Lee; Hoon Choi; Tae-Hoon Kim; Seungjong Lee; Nara Won; Yung-Hei Lee; In-Cheol Park; Chong-Min Kyung (ASP-DAC, 1997)

A C-Based RTL Design Verification Methodology for Complex Microprocessor. - Joon-Seo Yim; Yoon-Ho Hwang; Chang-Jae Park; Hoon Choi; Woo-Seung Yang; Hun-Seung Oh; In-Cheol Park; Chong-Min Kyung (DAC, 1997)

Design Verification of Complex Microprocessors. - Joon-Seo Yim; Chang-Jae Park; In-Cheol Park; Chong-Min Kyung (J. Circuits Syst. Comput., 1997)

Virtual Chip: Making Functional Models Work on Real Target Systems. - Namseung Kim; Hoon Choi; Seungjong Lee; Seungwang Lee; In-Cheol Park; Chong-Min Kyung (DAC, 1998)

MetaCore: An Application Specific DSP Development System. - Jin-Hyuk Yang; Byoung-Woon Kim; Sang-Jun Nam; Jang-Ho Cho; Sung-Won Seo; Chang-Ho Ryu; Young-Su Kwon; Dae-Hyun Lee; Jong-Yeol Lee; Jong-Sun Kim; Hyun-Dhong Yoon; Jae-Yeol Kim; et al. (DAC, 1998)

Multiple Behavior Module Synthesis Based on Selective Groupings. - Ju Hwan Yi; Hoon Choi; In-Cheol Park; Seung Ho Hwang; Chong-Min Kyung (DATE, 1998)

Synthesis of application specific instructions for embedded DSP software. - Hoon Choi; Seung Ho Hwang; Chong-Min Kyung; In-Cheol Park (ICCAD, 1998)

Node Sampling Technique to Speed Up Probability-Based Power Estimation Methods. - Hoon Choi; Hansoo Kim; In-Cheol Park; Seung Ho Hwang; Chong-Min Kyung (ASP-DAC, 1999)

A New Single-Clock Flip-Clop for Half-Swing Clocking. - Young-Su Kwon; Bong-Il Park; In-Cheol Park; Chong-Min Kyung (ASP-DAC, 1999)

Verification of a Microprocessor Using Real World Applications. - You-Sung Chang; Seungjong Lee; In-Cheol Park; Chong-Min Kyung (DAC, 1999)

Exploiting Intellectual Properties in ASIP Designs for Embedded DSP Software. - Hoon Choi; Ju Hwan Yi; Jong-Yeol Lee; In-Cheol Park; Chong-Min Kyung (DAC, 1999)

Customization of a CISC Processor Core for Low-Power Applications. - You-Sung Chang; Bong-Il Park; In-Cheol Park; Chong-Min Kyung (ICCD, 1999)

A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders. - Bong-Il Park; In-Cheol Park; Chong-Min Kyung (ICCD, 1999)

Path-based branch prediction using signature analysis. - Seunjeogn Lee; In-Cheol Park; Chong-Min Kyung (Microprocess. Microsystems, 1999)

Synthesis of Application Specific Instructions for Embedded DSP Software. - Hoon Choi; Jong-Sun Kim; Chi-Won Yoon; In-Cheol Park; Seung Ho Hwang; Chong-Min Kyung (IEEE Trans. Computers, 1999)

A hardware accelerator for the specular intensity of phong illumination model in 3-dimensional graphics. - Young-Su Kwon; In-Cheol Park; Chong-Min Kyung (ASP-DAC, 2000)

Multi-thread VLIW processor architecture for HDTV decoding. - Hansoo Kim; Woo-Seung Yang; Myoung-Cheol Shin; Seung-Jai Min; Seong-Ok Bae; In-Cheol Park (CICC, 2000)

FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders. - Hyeong-Ju Kang; Hansoo Kim; In-Cheol Park (ICCAD, 2000)

Synthesis and Optimization of Interface Hardware between IP's Operating at Different Clock Frequencies. - Bong-Il Park; Hoon Choi; In-Cheol Park; Chong-Min Kyung (ICCD, 2000)

Pyramid Texture Compression and Decompression Using Interpolative Vector Quantization. - Young-Su Kwon; In-Cheol Park; Chong-Min Kyung (ICIP, 2000)

Array address translation for SDRAM-based video processing applications. - Hansoo Kim; In-Cheol Park (VCIP, 2000)

Optimal down-conversion in compressed DCT domain with minimal operations. - Myoung-Cheol Shin; In-Cheol Park (VCIP, 2000)

MetaCore: an application-specific programmable DSP development system. - Jin-Hyuk Yang; Byoung-Woon Kim; Sang-Joon Nam; Young-Su Kwon; Dae-Hyun Lee; Jong-Yeol Lee; Chan-Soo Hwang; Yong Hoon Lee; Seung Ho Hwang; In-Cheol Park; Chong-Min Kyung (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Low-power high-level synthesis using latches. - Woo-Seung Yang; In-Cheol Park; Chong-Min Kyung (ASP-DAC, 2001)

Digital Filter Synthesis Based on Minimal Signed Digit Representation. - In-Cheol Park; Hyeong-Ju Kang (DAC, 2001)

An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking. - Myoung-Cheol Shin; Se-Hyeon Kang; In-Cheol Park (ICCD, 2001)

Multiplier-less IIR filter synthesis algorithms to trade-off the delay and the number of adders. - Hyeong-Ju Kang; In-Cheol Park (ISCAS (2), 2001)

Global variable localization and transformation for hardware synthesis from high-level programming language description. - Jong-Yeol Lee; In-Cheol Park (ISCAS (5), 2001)

A low-power variable length decoder based on successive decoding of shoft codewords. - Sung-Won Lee 005; In-Cheol Park (ISCAS (4), 2001)

A fixed-point MPEG audio processor operating at low frequency. - Yongseok Yi; In-Cheol Park (IEEE Trans. Consumer Electron., 2001)

High-performance and low-power memory-interface architecture for video processing applications. - Hansoo Kim; In-Cheol Park (IEEE Trans. Circuits Syst. Video Technol., 2001)

Timed compiled-code simulation of embedded software for performance analysis of SOC design. - Jong-Yeol Lee; In-Cheol Park (DAC, 2002)

A high-speed and low-latency Reed-Solomon decoder based on a dual-line structure. - Hyeong-Ju Kang; In-Cheol Park (ICASSP, 2002)

Low cost floating-point unit design for audio applications. - Sung-Won Lee 005; In-Cheol Park (ISCAS (1), 2002)

Area-efficient digital baseband module for Bluetooth wireless communications. - Myoung-Cheol Shin; Seong-Il Park; Sung-Won Lee 005; Se-Hyeon Kang; In-Cheol Park (ISCAS (5), 2002)

Loop and Address Code Optimization for Digital Signal Processors. - Jong-Yeol Lee; In-Cheol Park (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

An Automatic Interface Insertion Scheme for In-System Verification of Algorithm Models in C. - Chang-Jae Park; Ando Ki; In-Cheol Park; Chong-Min Kyung (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Interface synthesis between software chip model and target board. - Seungjong Lee; Ando Ki; In-Cheol Park; Chong-Min Kyung (J. Syst. Archit., 2002)

Digital filter synthesis based on an algorithm to generate all minimal signed digit representations. - In-Cheol Park; Hyeong-Ju Kang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Low-power hybrid structure of digital matched filters for direct sequence spread spectrum systems. - Sung-Won Lee 005; In-Cheol Park (ICASSP (2), 2003)

Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation. - In-Cheol Park; Se-Hyeon Kang; Yongseok Yi (ICCAD, 2003)

A 5-GHz self-calibrated I/Q clock generator using a quadrature LC-VCO. - Hyung Ki Ahn; In-Cheol Park; Beomsup Kim (ISCAS (1), 2003)

Pairing and ordering to reduce hardware complexity in cascade form filter design. - Hyeong-Ju Kang; In-Cheol Park (ISCAS (4), 2003)

A 24-bit floating-point audio DSP controller supporting fast exponentiation. - Sung-Won Lee 005; Hyeong-Ju Kang; In-Cheol Park (ISCAS (2), 2003)

Area-efficient memory-based architecture for FFT processing. - Sang-Chul Moon; In-Cheol Park (ISCAS (5), 2003)

History-based memory mode prediction for improving memory performance. - Seong-Il Park; In-Cheol Park (ISCAS (5), 2003)

A hybrid delta-sigma modulator with adaptive calibration. - Jae Hoon Shim; In-Cheol Park; Beomsup Kim (ISCAS (1), 2003)

Processor-based turbo interleaver for multiple third-generation wireless standards. - Myoung-Cheol Shin; In-Cheol Park (IEEE Commun. Lett., 2003)

A single-chip programmable platform based on a multithreaded processor and configurable logic clusters. - Young-Don Bae; Seong-Il Park; In-Cheol Park (IEEE J. Solid State Circuits, 2003)

Timed compiled-code functional simulation of embedded software for performance analysis of SOC design. - Jong-Yeol Lee; In-Cheol Park (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

A low-power variable length decoder for MPEG-2 based on successive decoding of short codewords. - Sung-Won Lee 005; In-Cheol Park (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

High performance memory mode control for HDTV decoders. - Seong-Il Park; Yongseok Yi; In-Cheol Park (IEEE Trans. Consumer Electron., 2003)

Address code generation for DSP instruction-set architectures. - Jong-Yeol Lee; In-Cheol Park (ACM Trans. Design Autom. Electr. Syst., 2003)

A 4.75GOPS single-chip programmable processor array consisting of a multithreaded processor and multiple SIMD and IO processors. - Young-Don Bae; In-Cheol Park (CICC, 2004)

Memory-based low density parity check code decoder architecture using loosely coupled two data-flows. - Se-Hyeon Kang; In-Cheol Park (ISCAS (2), 2004)

A fast Reed-Solomon Product-Code decoder without redundant computations. - Hyun-Yong Lee; In-Cheol Park (ISCAS (2), 2004)

Quadrature direct digital frequency synthesis using fine-grain angle rotation. - Sung-Won Lee 005; In-Cheol Park (ISCAS (2), 2004)

A scalable SIMD digital signal processor for high-quality multifunctional printer systems. - Hyeong-Ju Kang; Yongwoo Choi; Kimo Kim; In-Cheol Park; Jung-Wook Kim; Eul-Hwan Lee; Goo-Soo Gahang (Color Imaging: Processing, Hardcopy, and Applications, 2005)

Low-power log-MAP turbo decoding based on reduced metric memory access. - Dong-Soo Lee; In-Cheol Park (ISCAS (4), 2005)

Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation. - In-Cheol Park; Se-Hyeon Kang (ISCAS (6), 2005)

A Low-Complexity Stopping Criterion for Iterative Turbo Decoding. - Dong-Soo Lee; In-Cheol Park (IEICE Trans. Commun., 2005)

A third-order ΣΔ modulator in 0.18-μm CMOS with calibrated mixed-mode integrators. - Jae Hoon Shim; In-Cheol Park; Beomsup Kim (IEEE J. Solid State Circuits, 2005)

Correction to "A Third-Order$Sigma Delta $Modulator in 0.18-$muhboxm$CMOS With Calibrated Mixed-Mode Integrators". - Jae Hoon Shim; In-Cheol Park; Beomsup Kim (IEEE J. Solid State Circuits, 2005)

Performance enhancement of embedded software based on new register allocation technique. - Jong-Yeol Lee; Seong Ik Cho; In-Cheol Park (Microprocess. Microsystems, 2005)

SAT-based unbounded symbolic model checking. - Hyeong-Ju Kang; In-Cheol Park (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Hybrid ΣΔ modulators with adaptive calibration. - Jae Hoon Shim; In-Cheol Park; Beomsup Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

High speed decoding of context-based adaptive binary arithmetic codes using most probable symbol prediction. - Chung-Hyo Kim; In-Cheol Park (ISCAS, 2006)

Combined image signal processing for CMOS image sensors. - Kimo Kim; In-Cheol Park (ISCAS, 2006)

Low-Power Hybrid Turbo Decoding Based on Reverse Calculation. - Hye-Mi Choi; Ji-Hoon Kim 003; In-Cheol Park (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Loosely coupled memory-based decoding architecture for low density parity check codes. - Se-Hyeon Kang; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

Low-power log-MAP decoding based on reduced metric memory access. - Dong-Soo Lee; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

Twiddle factor transformation for pipelined FFT processing. - In-Cheol Park; WonHee Son; Ji-Hoon Kim 003 (ICCD, 2007)

High Speed Sphere Decoding Based on Vertically Incremental Computation. - Se-Hyeon Kang; In-Cheol Park (ISCAS, 2007)

Energy-Efficient Double-Binary Tail-Biting Turbo Decoder Based on Border Metric Encoding. - Ji-Hoon Kim 003; In-Cheol Park (ISCAS, 2007)

Tiled Interleaving for Multi-Level 2-D Discrete Wavelet Transform. - Jung-Wook Kim; Jinook Song; Seokho Lee; In-Cheol Park (ISCAS, 2007)

Two-Step Aprroach for Coarse Time Synchronization and Frequency Offset Estimation for IEEE 802.16D Systems. - Tae-Hwan Kim; In-Cheol Park (SiPS, 2007)

Fast and Area-Efficient Sphere Decoding Using Look-Ahead Search. - Se-Hyeon Kang; In-Cheol Park (VTC Spring, 2007)

Long-Point FFT Processing Based on Twiddle Factor Table Reduction. - Ji-Hoon Kim 003; In-Cheol Park (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Parallel Decoding of Context-Based Adaptive Binary Arithmetic Codes Based on Most Probable Symbol Prediction. - Chung-Hyo Kim; In-Cheol Park (IEICE Trans. Inf. Syst., 2007)

Pipelined Cartesian-to-Polar Coordinate Conversion Based on SRT Division. - Sung-Won Lee 005; Ki-Seok Kwon; In-Cheol Park (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Balanced Binary-Tree Decomposition for Area-Efficient Pipelined FFT Processing. - Hyun-Yong Lee; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

High-Speed H.264/AVC CABAC Decoding. - Y. Yi; In-Cheol Park (IEEE Trans. Circuits Syst. Video Technol., 2007)

SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards. - Myoung-Cheol Shin; In-Cheol Park (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Duo-binary circular turbo decoder based on border metric encoding for WiMAX. - Ji-Hoon Kim 003; In-Cheol Park (ASP-DAC, 2008)

Area and power efficient design of coarse time synchronizer and frequency offset estimator for fixed WiMAX systems. - Tae-Hwan Kim; In-Cheol Park (ASP-DAC, 2008)

Digital filter synthesis considering multiple adder graphs for a coefficient. - Jeong-Ho Han; In-Cheol Park (ICCD, 2008)

Fast frequency acquisition all-digital PLL using PVT calibration. - Hae-Soo Jeon; Duk-Hyun You; In-Cheol Park (ISCAS, 2008)

Capacitor array structure and switch control for energy-efficient SAR analog-to-digital converters. - Jeong-Sup Lee; In-Cheol Park (ISCAS, 2008)

Prediction-based real-time CABAC decoder for high definition H.264/AVC. - WonHee Son; In-Cheol Park (ISCAS, 2008)

Time-Domain Joint Estimation of Fine Symbol Timing Offset and Integer Carrier Frequency Offset. - Tae-Hwan Kim; In-Cheol Park (VTC Spring, 2008)

FIR Filter Synthesis Considering Multiple Adder Graphs for a Coefficient. - Jeong-Ho Han; In-Cheol Park (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Double-Binary Circular Turbo Decoding Based on Border Metric Encoding. - Ji-Hoon Kim 003; In-Cheol Park (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Low-Power and High-Accurate Synchronization for IEEE 802.16d Systems. - Tae-Hwan Kim; In-Cheol Park (IEEE Trans. Very Large Scale Integr. Syst., 2008)

A unified parallel radix-4 turbo decoder for mobile WiMAX and 3GPP-LTE. - Ji-Hoon Kim 003; In-Cheol Park (CICC, 2009)

Implementation of a High-Throughput and Area-Efficient MIMO Detector Based on Modified Dijkstra's Search. - Tae-Hwan Kim; In-Cheol Park (GLOBECOM, 2009)

Multiplier-less and table-less linear approximation for square and square-root. - In-Cheol Park; Tae-Hwan Kim (ICCD, 2009)

Architecture design of a high-performance dual-symbol binary arithmetic coder for JPEG2000. - Minsoo Rhu; In-Cheol Park (ICIP, 2009)

Memory-less bit-plane coder architecture for JPEG2000 with concurrent column-stripe coding. - Minsoo Rhu; In-Cheol Park (ICIP, 2009)

A Scalable and Programmable Sound Synthesizer. - Tae-Hwan Kim; Youngjoo Lee; In-Cheol Park (ISCAS, 2009)

Fast Frequency Acquisition Phase Frequency Detectors with Prediction-based edge Blocking. - Kangwoo Park; In-Cheol Park (ISCAS, 2009)

Novel Pipelined DWT Architecture for Dual-line Scan. - Jinook Song; In-Cheol Park (ISCAS, 2009)

A novel trace-pipelined binary arithmetic coder architecture for JPEG2000. - Minsoo Rhu; In-Cheol Park (SiPS, 2009)

Bit-Level Extrinsic Information Exchange Method for Double-Binary Turbo Codes. - Ji-Hoon Kim 003; In-Cheol Park (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Pipelined Discrete Wavelet Transform Architecture Scanning Dual Lines. - Jinook Song; In-Cheol Park (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A 2.6Gb/s 1.56mm2 near-optimal MIMO detector in 0.18µm CMOS. - Tae-Hwan Kim; In-Cheol Park (CICC, 2010)

Low-complex BPSK demodulation using absolute comparison. - Youngjoo Lee; Goeun Lim; In-Cheol Park (ICECS, 2010)

Dual-rail decoding of low-density parity-check codes. - Bongjin Kim; Hasan Ahmed; In-Cheol Park (ISCAS, 2010)

Capacitor array structure and switching control scheme to reduce capacitor mismatch effects for SAR analog-to-digital converters. - Youngjoo Lee; In-Cheol Park (ISCAS, 2010)

Low-complexity tone reservation method for PAPR reduction of OFDM systems. - Kangwoo Park; In-Cheol Park (ISCAS, 2010)

Small-area and low-energy K-best MIMO detector using relaxed tree expansion and early forwarding. - Tae-Hwan Kim; In-Cheol Park (ISLPED, 2010)

Multiplier-less and Table-less Linear Approximation for Square-Related Functions. - In-Cheol Park; Tae-Hwan Kim (IEICE Trans. Inf. Syst., 2010)

High-Throughput and Area-Efficient MIMO Symbol Detection Based on Modified Dijkstra's Search. - Tae-Hwan Kim; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Small-Area and Low-Energy K -Best MIMO Detector Using Relaxed Tree Expansion and Early Forwarding. - Tae-Hwan Kim; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Spur-Free MASH Delta-Sigma Modulation. - Jinook Song; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Optimization of Arithmetic Coding for JPEG2000. - Minsoo Rhu; In-Cheol Park (IEEE Trans. Circuits Syst. Video Technol., 2010)

Design of a Scalable and Programmable Sound Synthesizer. - Tae-Hwan Kim; Youngjoo Lee; In-Cheol Park (IEEE Trans. Very Large Scale Integr. Syst., 2010)

QC-LDPC Decoding Architecture based on Stride Scheduling. - Bongjin Kim; In-Cheol Park (ISCAS, 2011)

Statistical modeling of capacitor mismatch effects for successive approximation register ADCs. - Youngjoo Lee; Jinook Song; In-Cheol Park (ISOCC, 2011)

Division-less high-radix interleaved modular multiplication using a scaled modulus. - Jinook Song; In-Cheol Park (ISOCC, 2011)

Efficient Pruning for Infinity-Norm Sphere Decoding Based on Schnorr-Euchner Enumeration. - Tae-Hwan Kim; In-Cheol Park (IEICE Trans. Commun., 2011)

Low-Complexity Parallel Chien Search Structure Using Two-Dimensional Optimization. - Youngjoo Lee; Hoyoung Yoo; In-Cheol Park (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

Small-area parallel syndrome calculation for strong BCH decoding. - Youngjoo Lee; Hoyoung Yoo; In-Cheol Park (ICASSP, 2012)

Low-latency area-efficient decoding architecture for shortened reed-solomon codes. - Hoyoung Yoo; Youngjoo Lee; In-Cheol Park (ISOCC, 2012)

6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers. - Youngjoo Lee; Hoyoung Yoo; Injae Yoo; In-Cheol Park (ISSCC, 2012)

SNR-Adaptive Input Quantization for Turbo Decoding. - Injae Yoo; In-Cheol Park (VTC Spring, 2012)

Immediate Exchange of Extrinsic Information for High-Throughput Turbo Decoding. - Injae Yoo; Bongjin Kim; In-Cheol Park (IEEE Commun. Lett., 2012)

FIR Filter Synthesis Based on Interleaved Processing of Coefficient Generation and Multiplier-Block Synthesis. - Byeong Yong Kong; In-Cheol Park (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Low-Complexity Tone Reservation for PAPR Reduction in OFDM Communication Systems. - Kangwoo Park; In-Cheol Park (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A 3Gb/s 2.08mm2 100b error-correcting BCH decoder in 0.13µm CMOS process. - Youngjoo Lee; Hoyoung Yoo; In-Cheol Park (ASP-DAC, 2013)

Adaptive Metric Calculation for Improving Detection Capability of MIMO Detectors. - Byeong Yong Kong; In-Cheol Park (VTC Spring, 2013)

Memory-Optimized Hybrid Decoding Method for Multi-Rate Turbo Codes. - Injae Yoo; Bongjin Kim; In-Cheol Park (VTC Spring, 2013)

Efficient Tree-Traversal Strategy for Soft-Output MIMO Detection Based on Candidate-Set Reorganization. - Byeong Yong Kong; In-Cheol Park (IEEE Commun. Lett., 2013)

Area-Efficient QC-LDPC Decoder Architecture Based on Stride Scheduling and Memory Bank Division. - Bongjin Kim; In-Cheol Park (IEICE Trans. Commun., 2013)

A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory. - Youngjoo Lee; Hoyoung Yoo; Jaehwan Jung; Jihyuck Jo; In-Cheol Park (IEEE J. Solid State Circuits, 2013)

Low-Complexity Parallel QPP Interleaver Based on Permutation Patterns. - Bongjin Kim; Injae Yoo; In-Cheol Park (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Area-Efficient Multimode Encoding Architecture for Long BCH Codes. - Hoyoung Yoo; Jaehwan Jung; Jihyuck Jo; In-Cheol Park (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

7.3 Gb/s universal BCH encoder and decoder for SSD controllers. - Hoyoung Yoo; Youngjoo Lee; In-Cheol Park (ASP-DAC, 2014)

A search-less DEC BCH decoder for low-complexity fault-tolerant systems. - Injae Yoo; In-Cheol Park (SiPS, 2014)

Tail-Overlapped SISO Decoding for High-Throughput LTE-Advanced Turbo Decoders. - Injae Yoo; Bongjin Kim; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes. - Byeong Yong Kong; Jihyuck Jo; Hyewon Jeong; Mina Hwang; Soyoung Cha; Bongjin Kim; In-Cheol Park (IEEE Trans. Very Large Scale Integr. Syst., 2014)

High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives. - Youngjoo Lee; Hoyoung Yoo; Injae Yoo; In-Cheol Park (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Narrow-range frequency estimation based on comprehensive optimization of DFT and interpolation. - Byeong Yong Kong; In-Cheol Park (ICASSP, 2015)

Unidirectional ring ethernet for low-complexity in-vehicle control network. - Injae Yoo; Mina Hwang; Jaehwan Jung; Suhyun Kim; In-Cheol Park (ICIT, 2015)

Efficient Parallel Architecture for Linear Feedback Shift Registers. - Jaehwan Jung; Hoyoung Yoo; Youngjoo Lee; In-Cheol Park (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Low-Complexity Tree Architecture for Finding the First Two Minima. - Youngjoo Lee; Bongjin Kim; Jaehwan Jung; In-Cheol Park (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Reverse Rate Matching for Low-Power LTE-Advanced Turbo Decoders. - Injae Yoo; Bongjin Kim; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Partially Parallel Encoder Architecture for Long Polar Codes. - Hoyoung Yoo; In-Cheol Park (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Low-complexity symbol detection for massive MIMO uplink based on Jacobi method. - Byeong Yong Kong; In-Cheol Park (PIMRC, 2016)

Efficient Pruning for Successive-Cancellation Decoding of Polar Codes. - Hoyoung Yoo; In-Cheol Park (IEEE Commun. Lett., 2016)

Energy-Scalable 4KB LDPC Decoding Architecture for NAND-Flash-Based Storage Systems. - Youngjoo Lee; Jaehwan Jung; In-Cheol Park (IEICE Trans. Electron., 2016)

Area-Efficient Approach for Generating Quantized Gaussian Noise. - Jaejoon Choi; Jaehwan Jung; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Efficient Sorting Architecture for Successive-Cancellation-List Decoding of Polar Codes. - Byeong Yong Kong; Hoyoung Yoo; In-Cheol Park (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Low-Power Parallel Chien Search Architecture Using a Two-Step Approach. - Hoyoung Yoo; Youngjoo Lee; In-Cheol Park (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems. - Jihyuck Jo; Hoyoung Yoo; In-Cheol Park (IEEE Trans. Very Large Scale Integr. Syst., 2016)

An energy-optimized (37840, 34320) symmetric BC-BCH decoder for healthy mobile storages. - Seokha Hwang; Jaehwan Jung; Daesung Kim; Jeongseok Ha; In-Cheol Park; Youngjoo Lee (A-SSCC, 2017)

Improved Successive-Cancellation Decoding of Polar Codes Based on Recursive Syndrome Decomposition. - Jaejoon Choi; In-Cheol Park (IEEE Commun. Lett., 2017)

Multi-Bit Flipping Decoding of LDPC Codes for NAND Storage Systems. - Jaehwan Jung; In-Cheol Park (IEEE Commun. Lett., 2017)

Improved Hard-Reliability Based Majority-Logic Decoding for Non-Binary LDPC Codes. - Saedong Yeo; In-Cheol Park (IEEE Commun. Lett., 2017)

Low-Latency Low-Cost Architecture for Square and Cube Roots. - Jihyuck Jo; In-Cheol Park (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Improved Sorting Architecture for K-Best MIMO Detection. - Byeong Yong Kong; In-Cheol Park (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

High-Performance Low-Area Video Up-Scaling Architecture for 4-K UHD Video. - Jooseung Lee; In-Cheol Park (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Low-Power LDPC-CC Decoding Architecture Based on the Integration of Memory Banks. - Injae Yoo; In-Cheol Park (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A 2.4pJ/bit, 6.37Gb/s SPC-enhanced BC-BCH decoder in 65nm CMOS for NAND flash storage systems. - Jaehwan Jung; In-Cheol Park; Youngjoo Lee (ASP-DAC, 2018)

Interference Cancellation Architecture for Pipelined Parallel MIMO Detectors. - Byeong Yong Kong; Jaehwan Jung; In-Cheol Park (ICECS, 2018)

Efficient Implementation of Multiple Interleavers in IDMA for 5G. - Byeong Yong Kong; In-Cheol Park (ISOCC, 2018)

DSIP: A Scalable Inference Accelerator for Convolutional Neural Networks. - Jihyuck Jo; Soyoung Cha; Dayoung Rho; In-Cheol Park (IEEE J. Solid State Circuits, 2018)

A Memory-Efficient IDMA Architecture Based on On-the-Fly Despreading. - Byeong Yong Kong; In-Cheol Park (IEEE J. Solid State Circuits, 2018)

Energy-Efficient Convolution Architecture Based on Rescheduled Dataflow. - Jihyuck Jo; Suchang Kim; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Fast Low-Complexity Triple-Error-Correcting BCH Decoding Architecture. - Daesung Kim; Injae Yoo; In-Cheol Park (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Fast Successive Cancellation List Decoder for Polar Codes With an Early Stopping Criterion. - Daesung Kim; In-Cheol Park (IEEE Trans. Signal Process., 2018)

Parallel IDMA Architecture Based on Interleaving with Replicated Subpatterns. - Byeong Yong Kong; In-Cheol Park (ICC, 2019)

Energy-Efficient Symmetric BC-BCH Decoder Architecture for Mobile Storages. - Seokha Hwang; Seungsik Moon; Jaehwan Jung; Daesung Kim; In-Cheol Park; Jeongseok Ha; Youngjoo Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Large-Small Sorting for Successive Cancellation List Decoding of Polar Codes. - Kyungpil Lee; In-Cheol Park (IEEE Access, 2020)

Retrain-Less Weight Quantization for Multiplier-Less Convolutional Neural Networks. - Jaewoong Choi; Byeong Yong Kong; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A Low-Latency Multi-Touch Detector Based on Concurrent Processing of Redesigned Overlap Split and Connected Component Analysis. - Byeong Yong Kong; Jooseung Lee; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A 120-mW 0.16-ms-Latency Connectivity-Scalable Multiuser Detector for Interleave Division Multiple Access. - Byeong Yong Kong; In-Cheol Park (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Interleaved Local Sorting for Successive Cancellation List Decoding of Polar Codes. - Wooyoung Kim; Yujin Hyun; Jaeyoung Lee 004; In-Cheol Park (IEEE Access, 2021)

Hybrid Convolution Architecture for Energy-Efficient Deep Neural Network Processing. - Suchang Kim; Jihyuck Jo; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Constant-Time Synchronous Binary Counter With Minimal Clock Period. - Yujin Hyun; In-Cheol Park (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Real-Time SSDLite Object Detection on FPGA. - Suchang Kim; Seungho Na; Byeong Yong Kong; Jaewoong Choi; In-Cheol Park (IEEE Trans. Very Large Scale Integr. Syst., 2021)

In Situ Multi-Bit Decision for Successive Cancellation List Decoding of Polar Codes. - Jaehyeon Park; Jaeyoung Lee 004; In-Cheol Park (IEEE Access, 2022)

Multi-Mode QC-LDPC Decoding Architecture With Novel Memory Access Scheduling for 5G New-Radio Standard. - Seongjin Lee; Sangsoo Park; Boseon Jang; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

High-Speed Counter With Novel LFSR State Extension. - Hyungjoon Bae 001; Yujin Hyun; Suchang Kim; Sangsoo Park; Jaeyoung Lee 004; Boseon Jang; Suyoung Choi; In-Cheol Park (IEEE Trans. Computers, 2023)

A CNN Inference Accelerator on FPGA With Compression and Layer-Chaining Techniques for Style Transfer Applications. - Suchang Kim; Boseon Jang; Jaeyoung Lee 004; Hyungjoon Bae 001; Hyejung Jang; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Area-Efficient QC-LDPC Decoding Architecture With Thermometer Code-Based Sorting and Relative Quasi-Cyclic Shifting. - Boseon Jang; Hyejung Jang; Sungho Kim; Kangjoon Choi; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Hardware-Efficient SoftMax Architecture With Bit-Wise Exponentiation and Reciprocal Calculation. - Jeongmin Kim; Sungho Kim; Kangjoon Choi; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Hardware-Friendly Approximation for Swish Activation and Its Implementation. - Kangjoon Choi; Sungho Kim; Jeongmin Kim; In-Cheol Park (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

High-Speed CMOS Synchronous Binary Counter With Constant Counting Rate. - Sungho Kim; Jeongmin Kim; In-Cheol Park (IEEE Access, 2025)

Multi-Bit Successive Cancellation List Decoding of Polar Codes Using One-Bit Error Boundary. - In-Cheol Park; Seungju Woo; Jaeyoung Lee 004; Minha Park; Sangbeom Park (IEEE Commun. Lett., 2025)

Hardware-Efficient Architecture for Multiple Quantized Gaussian Noise Generation. - Kangjoon Choi; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

Energy-Efficient Syndrome Calculation Architecture for BCH Decoders. - Jeongmin Kim; Jaehoon Kwon; Hansol Jeong; In-Cheol Park (IEEE Trans. Very Large Scale Integr. Syst., 2025)