SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling. - Keonhee Cho; Heekyung Choi; In Jun Jung; Ji Sang Oh; Tae Woo Oh; Ki-Ryong Kim; Giseok Kim; Taemin Choi; Changsoo Sim; Taejoong Song; Seong-Ook Jung (VLSI Circuits, 2021)

SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased With Technology Scaling. - Keonhee Cho; Heekyung Choi; In Jun Jung; Ji Sang Oh; Tae Woo Oh; Ki-Ryong Kim; Giseok Kim; Taemin Choi; Changsu Sim; Taejoong Song; Seong-Ook Jung (IEEE J. Solid State Circuits, 2022)

A Sneak Current Compensation Scheme With Offset Cancellation Sensing Circuit for ReRAM-Based Cross-Point Memory Array. - Tae-Hyun Kim; Byungkyu Song; In Jun Jung; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

High-Precision and Low-Power Offset Canceling Tri-State Sensing Latch in NAND Flash Memory. - Taeyun Lee; In Jun Jung; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

An Offset-Canceled Sense Amplifier for DRAMs With Hidden Offset-Cancellation Time and Boosted Internal-Voltage-Difference. - In Jun Jung; Tae-Hyun Kim; Keonhee Cho; Ki-Ryong Kim; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Charge-Domain 4T2C eDRAM Compute-in-Memory Macro With Enhanced Variation Tolerance and Low-Overhead Data Conversion Schemes. - In Jun Jung; Dohan Kim 005; Minyoung Jo; Dong Han Ko; Young Kyu Lee; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Contention-Free Wordline Supporting Circuit for High Wordline Resistance in Sub-10-nm SRAM Designs. - Tae-Hyun Kim; Juhyun Park; In Jun Jung; Hoonki Kim; Taejoong Song; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Dual-Input Stacked Inverter-Based Single-Ended DRAM Sense Amplifier Using BL Switches for Low-Power High-Speed Sensing. - Sehee Lim; In Jun Jung; Gi Seok Kim; Dong Han Ko; Sumin Lee; Seong-Ook Jung (IEEE J. Solid State Circuits, 2025)