A 16Gb 12.8Gb/s LPDDR6 SDRAM with 12-DQ/Sub-Channel Wide NRZ Signaling and Enhanced Reliability by Per-Row Activation Counting and Meta-Data Scheme. - Kiheung Kim; Hong-Joo Song; Youngdo Um; Jinhun Jang; Seungjun Lee; Ho-Seok Seol; Hye-Jung Kwon; Ji-Hwan Seol; Hoon Shin; Jaehyung Lee; JongMoon Choi; Sung-Woo Yoon; et al. (ISSCC, 2026)

15.10 A Vertical-Cell-Transistor-Based 4F2 DRAM with Cell-on-Peripheral Architecture Using Wafer-to-Wafer Hybrid Copper Bonding. - Hyunchul Yoon; Youngseok Park; Tae Jin Park; Suk Lae Kim; Seungjae Jung; Daesun Kim; Kyunghwan Kim; Yongjun Kim; KyuChang Kang; Bokyeon Won; Sang-Hoon Jung; Seunghan Woo; et al. (ISSCC, 2026)