The VLSI Implementation of a Reed-Solomon Encoder Using Berlekamp's Bit-Serial Multiplier Algorithm. - In-Shek Hsu; Irving S. Reed; Trieu-Kien Truong; Ke Wang; Chiunn-Shyong Ye; Leslie J. Deutsch (IEEE Trans. Computers, 1984)

VLSI residue multiplier modulo a Fermat number. - Irving S. Reed; Trieu-Kien Truong; Jaw John Chang; Howard M. Shao; In-Shek Hsu (IEEE Symposium on Computer Arithmetic, 1985)

The VLSI design of a single chip for the multiplication of integers modulo a Fermat number. - Jaw John Chang; Trieu-Kien Truong; Howard M. Shao; Irving S. Reed; In-Shek Hsu (IEEE Trans. Acoust. Speech Signal Process., 1985)

A single chip VLSI Reed-Solomon decoder. - Howard M. Shao; Trieu-Kien Truong; In-Shek Hsu; Leslie J. Deutsch; Irving S. Reed (ICASSP, 1986)

The VLSI Design of an Error-Trellis Syndrome Decoder for Certain Convolutional Codes. - Irving S. Reed; Trieu-Kien Truong; Jørn M. Jensen; In-Shek Hsu (IEEE Trans. Computers, 1986)

Techniques for Computing the Discrete Fourier Transform Using the Quadratic Residue Fermat Number Systems. - Trieu-Kien Truong; Jaw John Chang; In-Shek Hsu; D. Y. Pei; Irving S. Reed (IEEE Trans. Computers, 1986)

A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with fermat numbers. - Hsuen-Chyun Shyu; Trieu-Kien Truong; Irving S. Reed; In-Shek Hsu; Jaw John Chang (IEEE Trans. Acoust. Speech Signal Process., 1987)

A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases. - In-Shek Hsu; Trieu-Kien Truong; Leslie J. Deutsch; Irving S. Reed (IEEE Trans. Computers, 1988)

A Pipeline Design of a Fast Prime Factor DFT on a Finite Field. - Trieu-Kien Truong; Irving S. Reed; In-Shek Hsu; Hsuen-Chyun Shyu; Howard M. Shao (IEEE Trans. Computers, 1988)

An FPT algorithm with a modularized structure for computing 2-D cyclic convolutions. - Trieu-Kien Truong; D. Y. Pei; Irving S. Reed; Yao-Fang Chu; In-Shek Hsu (IEEE Trans. Acoust. Speech Signal Process., 1988)