1-bit full adder design using next generation semiconductor devices and performance benchmarking at low supply voltages. - S. Lakshmanachari; Sadulla Shaik; G. S. R. Satyanarayana; Inapudi Vasavi; Vallabhuni Vijay; Chandra Shaker Pittala (Int. J. Syst. Assur. Eng. Manag., 2024)