Efficient Fault Simulation of CMOS Circuits with Accurate Models. - Zeev Barzilai; J. Lawrence Carter; Vijay S. Iyengar; Indira Nair; Barry K. Rosen; Joe D. Rutledge; Gabriel M. Silberman (ITC, 1986)

Evaluating an information system for policy modeling and uncertainty analysis. - Max Henrion; M. Granger Morgan; Indira Nair; Charles Wiecha (J. Am. Soc. Inf. Sci., 1986)

Symbolic implication in test generation. - Sandip Kundu; Indira Nair; Leendert M. Huisman; Vijay S. Iyengar (EURO-DAC, 1991)

A Small Test Generator for Large Designs. - Sandip Kundu; Leendert M. Huisman; Indira Nair; Vijay S. Iyengar; Lakshmi N. Reddy (ITC, 1992)

Architectural Verification of Processors Using Symbolic Instruction Graphs. - Ashok K. Chandra; Vijay S. Iyengar; R. V. Jawalekar; Michael P. Mullen; Indira Nair; Barry K. Rosen (ICCD, 1994)

AVPGEN-A test generator for architecture verification. - Ashok K. Chandra; Vijay S. Iyengar; D. Jameson; R. V. Jawalekar; Indira Nair; Barry K. Rosen; Michael P. Mullen; J. Yoon; R. Armoni; Daniel Geist; Yaron Wolfsthal (IEEE Trans. Very Large Scale Integr. Syst., 1995)

Control-flow versus data-flow-based scheduling: combining both approaches in an adaptive scheduling system. - Reinaldo A. Bergamaschi; Salil Raje; Indira Nair; Louise Trevillyan (IEEE Trans. Very Large Scale Integr. Syst., 1997)

Early analysis tools for system-on-a-chip design. - John A. Darringer; Reinaldo A. Bergamaschi; Subhrajit Bhattacharya; Daniel Brand; Andreas Herkersdorf; Joseph K. Morrell; Indira Nair; Patricia Sagmeister; Youngsoo Shin (IBM J. Res. Dev., 2002)

SEAS: a system for early analysis of SoCs. - Reinaldo A. Bergamaschi; Youngsoo Shin; Nagu R. Dhanwada; Subhrajit Bhattacharya; William E. Dougherty; Indira Nair; John A. Darringer; Sarala Paliwal (CODES+ISSS, 2003)

An efficient system-on-a-chip design methodology for networking applications. - Valentina Salapura; Christos J. Georgiou; Indira Nair (CASES, 2004)

Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems. - Nagu R. Dhanwada; Reinaldo A. Bergamaschi; William W. Dungan; Indira Nair; Paul Gramann; William E. Dougherty; Ing-Chao Lin (Des. Autom. Embed. Syst., 2005)

Performance modeling for early analysis of multi-core systems. - Reinaldo A. Bergamaschi; Indira Nair; Gero Dittmann; Hiren D. Patel; Geert Janssen; Nagu R. Dhanwada; Alper Buyuktosunoglu; Emrah Acar; Gi-Joon Nam; Dorothy Kucar; Pradip Bose; John A. Darringer; et al. (CODES+ISSS, 2007)

Exploring power management in multi-core systems. - Reinaldo A. Bergamaschi; Guoling Han; Alper Buyuktosunoglu; Hiren D. Patel; Indira Nair; Gero Dittmann; Geert Janssen; Nagu R. Dhanwada; Zhigang Hu; Pradip Bose; John A. Darringer (ASP-DAC, 2008)

Power Management and Its Impact on Power Supply Noise. - Howard Chen 001; Indira Nair (PATMOS, 2009)

Power-efficient, reliable microprocessor architectures: modeling and design methods. - Pradip Bose; Alper Buyuktosunoglu; Chen-Yong Cher; John A. Darringer; Meeta Sharma Gupta; Hendrik F. Hamann; Hans M. Jacobson; Prabhakar Kudva; Eren Kursun; Niti Madan; Indira Nair; Jude A. Rivers; et al. (ACM Great Lakes Symposium on VLSI, 2010)

The Effect of Dynamic Power Management on Mid-Frequency and Low-Frequency Power Supply Noise. - Howard Chen 001; Indira Nair; Benjamin Mashak (J. Low Power Electron., 2010)

Power management of multi-core chips: Challenges and pitfalls. - Pradip Bose; Alper Buyuktosunoglu; John A. Darringer; Meeta Sharma Gupta; Michael B. Healy; Hans M. Jacobson; Indira Nair; Jude A. Rivers; Jeonghee Shin; Augusto Vega; Alan J. Weger (DATE, 2012)

IBM Blue Gene/Q memory subsystem with speculative execution and transactional memory. - Martin Ohmacht; Amy Wang; Thomas Gooding; Ben J. Nathanson; Indira Nair; Geert Janssen; Marcel Schaal; Burkhard D. Steinmacher-Burow (IBM J. Res. Dev., 2013)

Pragmatism and Care in Engineering Ethics. - Indira Nair; William M. Bulleit (Sci. Eng. Ethics, 2020)

14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (ISSCC, 2024)

Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (IEEE J. Solid State Circuits, 2025)