Thermal aware test scheduling for stacked multi-chip-modules. - N. S. Vinay; Indira Rawat; Erik Larsson; Manoj Singh Gaur; Virendra Singh (EWDTS, 2010)

Thermal analysis and modeling of 3D integrated circuits for test scheduling. - Indira Rawat; M. K. Gupta; Virendra Singh (3DIC, 2013)

Scheduling tests for 3D SoCs with temperature constraints. - Indira Rawat; M. K. Gupta; Virendra Singh (EWDTS, 2013)

Temperature aware test scheduling by modified floorplanning. - Indira Rawat; M. K. Gupta; Virendra Singh (EWDTS, 2014)