Design of an Application Specific VLSI Chip for Image Rotation. - Indradeep Ghosh; Bandana Majumdar (VLSI Design, 1994)

VLSI Implementation of An Efficient ASIC Architecture for Real-Time Rotation of Digital Images. - Indradeep Ghosh; Bandana Majumdar (Int. J. Pattern Recognit. Artif. Intell., 1995)

A design for testability technique for RTL circuits using control/data flow extraction. - Indradeep Ghosh; Anand Raghunathan; Niraj K. Jha (ICCAD, 1996)

Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs. - Indradeep Ghosh; Anand Raghunathan; Niraj K. Jha (DAC, 1997)

A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems. - Indradeep Ghosh; Niraj K. Jha; Sujit Dey (ITC, 1997)

A Practical Method for Selecting Partial Scan Flip-flops for Large Circuits. - Sudipta Bhawmik; Indradeep Ghosh (VLSI Design, 1997)

Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. - Indradeep Ghosh; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

A Fast and Low Cost Testing Technique for Core-Based System-on-Chip. - Indradeep Ghosh; Sujit Dey; Niraj K. Jha (DAC, 1998)

A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis. - Indradeep Ghosh; Niraj K. Jha; Sudipta Bhawmik (DAC, 1998)

Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits. - Srivaths Ravi 001; Indradeep Ghosh; Rabindra K. Roy; Sujit Dey (J. Electron. Test., 1998)

High-level test synthesis: a survey. - Indradeep Ghosh; Niraj K. Jha (Integr., 1998)

A design-for-testability technique for register-transfer level circuits using control/data flow extraction. - Indradeep Ghosh; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

A low overhead design for testability and test generation technique for core-based systems-on-a-chip. - Indradeep Ghosh; Niraj K. Jha; Sujit Dey (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Hierarchical test generation and design for testability methods for ASPPs and ASIPs. - Indradeep Ghosh; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Automatic test pattern generation for functional RTL circuits using assignment decision diagrams. - Indradeep Ghosh; Masahiro Fujita (DAC, 2000)

A Technique for Identifying RTL and Gate-Level Correspondences. - Srivaths Ravi 001; Niraj K. Jha; Indradeep Ghosh; Vamsi Boppana (ICCD, 2000)

Hierarchical Error Diagnosis Targeting RTL Circuits. - Vamsi Boppana; Indradeep Ghosh; Rajarshi Mukherjee; Jawahar Jain; Masahiro Fujita (VLSI Design, 2000)

A fast and low-cost testing technique for core-based system-chips. - Indradeep Ghosh; Sujit Dey; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

A BIST scheme for RTL circuits based on symbolic testabilityanalysis. - Indradeep Ghosh; Niraj K. Jha; Sudipta Bhawmik (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Observability enhanced coverage analysis of C programs for functional validation. - Farzan Fallah; Indradeep Ghosh (HLDVT, 2001)

Automatic test pattern generation for functional register-transferlevel circuits using assignment decision diagrams. - Indradeep Ghosh; Masahiro Fujita (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences. - Srivaths Ravi 001; Indradeep Ghosh; Vamsi Boppana; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Design for Verification at the Register Transfer Level. - Indradeep Ghosh; Krishna Sekar; Vamsi Boppana (ASP-DAC/VLSI Design, 2002)

Event-driven observability enhanced coverage analysis of C programs for functional validation. - Farzan Fallah; Indradeep Ghosh; Masahiro Fujita (ASP-DAC, 2003)

Automatic Design Validation Framework for HDL Descriptions via RTL ATPG. - Liang Zhang 012; Michael S. Hsiao; Indradeep Ghosh (Asian Test Symposium, 2003)

On automatic generation of RTL validation test benches using circuit testing techniques. - Indradeep Ghosh; Srivaths Ravi 001 (ACM Great Lakes Symposium on VLSI, 2003)

Precomputation-based Guarding for Dynamic and Leakage Power Reduction. - Afshin Abdollahi; Massoud Pedram; Farzan Fallah; Indradeep Ghosh (ICCD, 2003)

Efficient Sequential ATPG for Functional RTL Circuits. - Liang Zhang 012; Indradeep Ghosh; Michael S. Hsiao (ITC, 2003)

High Level Design Validation: Current Practices and Future Directions. - Indradeep Ghosh; Rajarshi Mukherjee; Mukul R. Prasad; Masahiro Fujita (VLSI Design, 2004)

High Level Test Generation for Custom Hardware: An Industrial Perspective. - Indradeep Ghosh (Asian Test Symposium, 2005)

A Technique for Estimating the Difficulty of a Formal Verification Problem. - Indradeep Ghosh; Mukul R. Prasad (ISQED, 2006)

A Framework for Automatic Design Validation of RTL Circuits Using ATPG and Observability-Enhanced Tag Coverage. - Liang Zhang 012; Indradeep Ghosh; Michael S. Hsiao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Verification Techniques for System-Level Design. - Masahiro Fujita; Indradeep Ghosh; Mukul R. Prasad (Morgan Kaufmann, 2008)

Context-Sensitive Relevancy Analysis for Efficient Symbolic Execution. - Xin Li 010; Daryl Shannon; Indradeep Ghosh; Mizuhito Ogawa; Sreeranga P. Rajan; Sarfraz Khurshid (APLAS, 2008)

WEAVE: WEb Applications Validation Environment. - Sreeranga P. Rajan; Oksana Tkachuk; Mukul R. Prasad; Indradeep Ghosh; Nitin Goel; Tadahiro Uehara (ICSE Companion, 2009)

KLOVER: A Symbolic Execution and Automatic Test Generation Tool for C++ Programs. - Guodong Li; Indradeep Ghosh; Sreeranga P. Rajan (CAV, 2011)

GKLEE: concolic verification and test generation for GPUs. - Guodong Li; Peng Li 058; Geoffrey Sawaya; Ganesh Gopalakrishnan; Indradeep Ghosh; Sreeranga P. Rajan (PPoPP, 2012)

PASS: String Solving with Parameterized Array and Interval Automaton. - Guodong Li; Indradeep Ghosh (Haifa Verification Conference, 2013)

Lazy Symbolic Execution through Abstraction and Sub-space Search. - Guodong Li; Indradeep Ghosh (Haifa Verification Conference, 2013)

JST: an automatic test generation tool for industrial Java applications with strings. - Indradeep Ghosh; Nastaran Shafiei; Guodong Li; Wei-Fan Chiang (ICSE, 2013)

SymJS: automatic symbolic testing of JavaScript web applications. - Guodong Li; Esben Andreasen; Indradeep Ghosh (SIGSOFT FSE, 2014)

Generating Succinct Test Cases Using Don't Care Analysis. - Cuong Nguyen 001; Hiroaki Yoshida; Mukul R. Prasad; Indradeep Ghosh; Koushik Sen (ICST, 2015)

FSX: fine-grained incremental unit test generation for C/C++ programs. - Hiroaki Yoshida; Susumu Tokumoto; Mukul R. Prasad; Indradeep Ghosh; Tadahiro Uehara (ISSTA, 2016)

FSX: a tool for fine-grained incremental unit test generation for C/C++ programs. - Hiroaki Yoshida; Susumu Tokumoto; Mukul R. Prasad; Indradeep Ghosh; Tadahiro Uehara (SIGSOFT FSE, 2016)

KLOVER: Automatic Test Generation for C and C Programs, Using Symbolic Execution. - Hiroaki Yoshida; Guodong Li; Takuki Kamiya; Indradeep Ghosh; Sreeranga P. Rajan; Susumu Tokumoto; Kazuki Munakata; Tadahiro Uehara (IEEE Softw., 2017)

Binary Matrix Factorization on Special Purpose Hardware. - Osman Asif Malik; Hayato Ushijima-Mwesigwa; Arnab Roy 001; Avradip Mandal; Indradeep Ghosh (CoRR, 2020)

Ising-Based Louvain Method: Clustering Large Graphs with Specialized Hardware. - Pouya Rezazadeh Kalehbasti; Hayato Ushijima-Mwesigwa; Avradip Mandal; Indradeep Ghosh (IDA, 2021)

Partitioning Dense Graphs with Hardware Accelerators. - Xiaoyuan Liu 001; Hayato Ushijima-Mwesigwa; Indradeep Ghosh; Ilya Safro (ICCS (3), 2022)

Towards Practical Explainability with Cluster Descriptors. - Xiaoyuan Liu 001; Ilya Tyagin; Hayato Ushijima-Mwesigwa; Indradeep Ghosh; Ilya Safro (ICDM (Workshops), 2022)

Scaling Vehicle Routing Problem Solvers with QUBO-based Specialized Hardware. - Hanjing Xu; Hayato Ushijima-Mwesigwa; Indradeep Ghosh (SEC, 2022)