An Improved Double Byte Error Correcting Code Using Cellular Automata. - Jaydeb Bhaumik; Dipanwita Roy Chowdhury; Indrajit Chakrabarti (ACRI, 2008)

A Parallel Architecture for Successive Elimination Block Matching Algorithm. - Kota Naga Srinivasarao Batta; Indrajit Chakrabarti (ICVGIP, 2008)

High Speed and Memory Efficient Parallel Bit Plane Coding Architecture for JPEG2000. - Tenugu Suman; Sumit Kumar Chatterjee; Indrajit Chakrabarti (ICVGIP, 2008)

A probabilistic adaptive algorithm for constructing hierarchical meshes. - Kalyan Goswami; Indrajit Chakrabarti; Shamik Sural (IEEE Trans. Consumer Electron., 2009)

Null Boundary 90/150 Cellular Automata for Multi-byte Error Correcting Code. - Jaydeb Bhaumik; Dipanwita Roy Chowdhury; Indrajit Chakrabarti (ACRI, 2010)

Multi-standard programmable baseband modulator for next generation wireless communication - Indranil Hatai; Indrajit Chakrabarti (CoRR, 2010)

Low power VLSI architectures for one bit transformation based fast motion estimation. - Sumit Kumar Chatterjee; Indrajit Chakrabarti (IEEE Trans. Consumer Electron., 2010)

An improved low-power high-throughput log-MAP turbo decoder. - Shaikh Montajul Karim; Indrajit Chakrabarti (IEEE Trans. Consumer Electron., 2010)

A New High-Performance Digital FM Modulator and Demodulator for Software-Defined Radio and Its FPGA Implementation. - Indranil Hatai; Indrajit Chakrabarti (Int. J. Reconfigurable Comput., 2011)

Power efficient motion estimation algorithm and architecture based on pixel truncation. - Sumit Kumar Chatterjee; Indrajit Chakrabarti (IEEE Trans. Consumer Electron., 2011)

High-throughput turbo decoder using pipelined parallel architecture and collision-free interleaver. - Shaikh Montajul Karim; Indrajit Chakrabarti (IET Commun., 2012)

Reconfigurable Architecture of a RRC Fir Interpolator for Multi-standard Digital Up Converter. - Indranil Hatai; Indrajit Chakrabarti; Swapna Banerjee (IPDPS Workshops, 2013)

Algorithm and architecture for quarter pixel motion estimation for H.264/AVC. - Sumit Kumar Chatterjee; Indrajit Chakrabarti (NCVPRIPG, 2013)

High performance VLSI implementation of Context-based Adaptive Variable Length Coding (CAVLC) for H.264 encoder. - R. Mukherjee; Vikrant Mahajan; Indrajit Chakrabarti; S. Sengupta (NCVPRIPG, 2013)

Decentralized cooperative spectrum sensing in cognitive radio without fusion centre. - Debasish Bera; Shobhit Maheshwari; Indrajit Chakrabarti; Sant Saran Pathak (NCC, 2014)

VLSI design of fast fractal image encoder. - Mamata Panigrahy; Indrajit Chakrabarti; Anindya Sundar Dhar (VDAT, 2014)

A phase-aware single channel speech enhancement technique using separate bayesian estimators for voiced and unvoiced regions with digital hearing aid application. - Suman Samui; Indrajit Chakrabarti; Soumya Kanti Ghosh 001 (HealthCom, 2015)

ZMesh: An Energy-Efficient Network-on-Chip Topology for Constant-Geometry Algorithms. - N. Prasad 001; Santanu Chattopadhyay; Indrajit Chakrabarti (iNIS, 2015)

Hardware implementation of Frequency Domain Link Adaptation for OFDMA based systems. - Sandip Das 003; Indrajit Chakrabarti; Suvra Sekhar Das (NCC, 2015)

Complexity assisted consistent quality rate control for high resolution H.264 video conferencing. - Subhomoy Bhattacharyya; Indrajit Chakrabarti; Maheshkumar H. Kolekar (NCVPRIPG, 2015)

Automated detection and classification of mass from breast ultrasound images. - Radhika V. Menon; Poulami Raha; Shweta Kothari; Sumit Chakraborty; Indrajit Chakrabarti; Rezaul Karim (NCVPRIPG, 2015)

Hardware Implementation of Compressed Sensing based Low Complex Video Encoder. - Kota Naga Srinivasarao Batta; Indrajit Chakrabarti (CoRR, 2015)

High Speed VLSI Architecture for 3-D Discrete Wavelet Transform. - Kota Naga Srinivasarao Batta; Indrajit Chakrabarti (CoRR, 2015)

High Performance VLSI Architecture for Three-Step Search Algorithm. - Rohan Mukherjee 002; Keyur Sheth; Anindya Sundar Dhar; Indrajit Chakrabarti; Somnath Sengupta (Circuits Syst. Signal Process., 2015)

High-speed low-power very-large-scale integration architecture for dual-standard deblocking filter. - Kota Naga Srinivasarao Batta; Indrajit Chakrabarti; Mohammad Nawaz Ahmad (IET Circuits Devices Syst., 2015)

Efficient architecture of adaptive rood pattern search technique for fast motion estimation. - Baishik Biswas; Rohan Mukherjee 002; Indrajit Chakrabarti (Microprocess. Microsystems, 2015)

Reconfigurable data parallel constant geometry fast Fourier transform architectures on Network-on-Chip. - N. Prasad 001; Santanu Chattopadhyay; Indrajit Chakrabarti (Microprocess. Microsystems, 2015)

An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis. - Indranil Hatai; Indrajit Chakrabarti; Swapna Banerjee (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation. - Indranil Hatai; Indrajit Chakrabarti; Swapna Banerjee (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Motion Estimation for Video Coding - Efficient Algorithms and Architectures - Indrajit Chakrabarti; Kota Naga Srinivasarao Batta; Sumit Kumar Chatterjee (Springer, 2015)

Hardware implementation of MIL-STD-1553 protocol over OFDMA-PHY based wireless high data rate avionics systems. - Sandip Das 003; Suvra Sekhar Das; Indrajit Chakrabarti (ANTS, 2016)

Two-Stage Temporal Processing for Single-Channel Speech Enhancement. - Suman Samui; Indrajit Chakrabarti; Soumya Kanti Ghosh 001 (INTERSPEECH, 2016)

Global soft decision based speech enhancement using voiced-unvoiced uncertainty and harmonic phase decomposition technique. - Suman Samui; Indrajit Chakrabarti; Soumya Kanti Ghosh 001 (SPCOM, 2016)

VLSI Friendly Framework for Scalable Video Coding based on Compressed Sensing. - Kota Naga Srinivasarao Batta; Vinay Chakravarthi Gogineni; Subrahmanyam Mula; Indrajit Chakrabarti (CoRR, 2016)

Low-Delay Parallel Architecture for Fractal Image Compression. - Mamata Panigrahy; Indrajit Chakrabarti; Anindya Sundar Dhar (Circuits Syst. Signal Process., 2016)

Very large scale integration architecture for block-matching motion estimation using adaptive rood pattern search algorithm. - Shiju Padmanabhan Puthenpurayil; Indrajit Chakrabarti; Rishi Virdi; Harsh Kaushik (IET Circuits Devices Syst., 2016)

Improved single channel phase-aware speech enhancement technique for low signal-to-noise ratio signal. - Suman Samui; Indrajit Chakrabarti; Soumya Kanti Ghosh 001 (IET Signal Process., 2016)

High Performance VISI Design of Diamond Search Algorithm for Fast Motion Estimation. - Rohan Mukherjee 002; Vikrant Mahajan; Anindya Sundar Dhar; Indrajit Chakrabarti (J. Circuits Syst. Comput., 2016)

Efficient VLSI design of adaptive rood pattern search algorithm for motion estimation of high definition videos. - Rohan Mukherjee 002; Baishik Biswas; Indrajit Chakrabarti; Pranab Kumar Dutta; Ajoy Kumar Ray (Microprocess. Microsystems, 2016)

Modelling of Cooperative Spectrum Sensing over Rayleigh Fading Without CSI in Cognitive Radio Networks. - Debasish Bera; Indrajit Chakrabarti; Sant Sharan Pathak (Wirel. Pers. Commun., 2016)

Real-time digitized neural-spike storage scheme in multiple channels for biomedical applications. - Anand Kumar Mukhopadhyay; Indrajit Chakrabarti; Mrigank Sharad (APSIPA, 2017)

Deep Recurrent Neural Network Based Monaural Speech Separation Using Recurrent Temporal Restricted Boltzmann Machines. - Suman Samui; Indrajit Chakrabarti; Soumya K. Ghosh 001 (INTERSPEECH, 2017)

Runtime mitigation of illegal packet request attacks in Networks-on-Chip. - N. Prasad 001; Rajit Karmakar; Santanu Chattopadhyay; Indrajit Chakrabarti (ISCAS, 2017)

Efficient VLSI design of CAVLC decoder of H.264 for HD videos. - Rohan Mukherjee 002; Anupam Banerjee; Indrajit Chakrabarti; Pranab Kumar Dutta; Ajoy Kumar Ray (ISED, 2017)

Improving the Performance of Deep Learning Based Speech Enhancement System Using Fuzzy Restricted Boltzmann Machine. - Suman Samui; Indrajit Chakrabarti; Soumya K. Ghosh 001 (PReMI, 2017)

Memory Efficient Fractal-SPIHT Based Hybrid Image Encoder. - Mamata Panigrahy; Nirmal Chandra Behera; B. Vandana; Indrajit Chakrabarti; Anindya Sundar Dhar (VDAT, 2017)

Speed-Area Optimized VLSI Architecture of Hexagonal Search Algorithm for Motion Estimation of (512×512) Frames. - Rohan Mukherjee 002; Baishik Biswas; Indrajit Chakrabarti; Pranab Kumar Dutta; Somnath Sengupta; Ajoy Kumar Ray (Circuits Syst. Signal Process., 2017)

FPGA Implementation of a Phase-Aware Single-Channel Speech Enhancement System. - Suman Samui; Pragya Sahu; Indrajit Chakrabarti; Soumya Kanti Ghosh 001 (Circuits Syst. Signal Process., 2017)

A novel framework for compressed sensing based scalable video coding. - Kota Naga Srinivasarao Batta; Vinay Chakravarthi Gogineni; Subrahmanyam Mula; Indrajit Chakrabarti (Signal Process. Image Commun., 2017)

Another Look in the Analysis of Cooperative Spectrum Sensing over Nakagami-m Fading Channels. - Debasish Bera; Indrajit Chakrabarti; Sant S. Pathak; George K. Karagiannidis (IEEE Trans. Wirel. Commun., 2017)

Classification of Hand Movements by Surface Myoelectric Signal Using Artificial-Spiking Neural Network Model. - Anand Kumar Mukhopadhyay; Indrajit Chakrabarti; Mrigank Sharad (IEEE SENSORS, 2018)

Power efficient Spiking Neural Network Classifier based on memristive crossbar network for spike sorting application. - Anand Kumar Mukhopadhyay; Indrajit Chakrabarti; Arindam Basu; Mrigank Sharad (CoRR, 2018)

Tensor-Train Long Short-Term Memory for Monaural Speech Enhancement. - Suman Samui; Indrajit Chakrabarti; Soumya K. Ghosh 001 (CoRR, 2018)

A High-Speed VLSI Architecture for Motion Estimation Using Modified Adaptive Rood Pattern Search Algorithm. - Baishik Biswas; Rohan Mukherjee 002; Indrajit Chakrabarti; Pranab Kumar Dutta; Ajoy Kumar Ray (Circuits Syst. Signal Process., 2018)

Fast adaptive motion estimation algorithm and its efficient VLSI system for high definition videos. - Rohan Mukherjee 002; Priyabrata Saha; Indrajit Chakrabarti; Pranab Kumar Dutta; Ajoy Kumar Ray (Expert Syst. Appl., 2018)

Design and evaluation of ZMesh topology for on-chip interconnection networks. - N. Prasad 001; Priyajit Mukherjee; Santanu Chattopadhyay; Indrajit Chakrabarti (J. Parallel Distributed Comput., 2018)

VLSI architecture for fixed mesh based deformable motion estimation using ARPS algorithm. - Shiju Padmanabhan Puthenpurayil; Indrajit Chakrabarti; Rishi Virdi; Snehal Wasnik (Microprocess. Microsystems, 2018)

A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical-Horizontal Common Sub-Expression Elimination Algorithm. - Indranil Hatai; Indrajit Chakrabarti; Swapna Banerjee (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

An Energy-Efficient Network-on-Chip-Based Reconfigurable Viterbi Decoder Architecture. - N. Prasad 001; Indrajit Chakrabarti; Santanu Chattopadhyay (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A Parallel Stochastic Number Generator With Bit Permutation Networks. - Vikash Sehwag; N. Prasad 001; Indrajit Chakrabarti (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Design of a Chaotic Oscillator based Model Building Attack Resistant Arbiter PUF. - Venkata Sreekanth Balijabudda; Dhruv Thapar; Pranesh Santikellur; Rajat Subhra Chakraborty; Indrajit Chakrabarti (AsianHOST, 2019)

Exploring Formaldehyde Sensing Capability of Noble Metal Decorated Reduced Graphene Oxide through First Principle Approach. - Bibhas Manna; Snehanjan Acharyya; Indrajit Chakrabarti; Prasanta Kumar Guha (IEEE SENSORS, 2019)

Design and Implementation of Threshold Logic Functions Using Memristors. - Yaswanth Krishna Yadav Danaboina; Pravanjan Samanta; Kamalika Datta; Indrajit Chakrabarti; Indranil Sengupta 001 (VLSID, 2019)

Time-frequency masking based supervised speech enhancement framework using fuzzy deep belief network. - Suman Samui; Indrajit Chakrabarti; Soumya K. Ghosh 001 (Appl. Soft Comput., 2019)

Runtime Mitigation of Packet Drop Attacks in Fault-tolerant Networks-on-Chip. - N. Prasad 001; Navonil Chatterjee; Santanu Chattopadhyay; Indrajit Chakrabarti (CoRR, 2019)

Intelligent Wireless Sensor Nodes for Human Footstep Sound Classification for Security Application. - Anand Kumar Mukhopadhyay; Naligala Moses Prabhakar; Divya Lakshmi Duggisetty; Indrajit Chakrabarti; Mrigank Sharad (CoRR, 2019)

High-throughput Bit Flipping decoder for structured LDPC codes. - Shantharam Kalipatnapu; Indrajit Chakrabarti (IET Commun., 2019)

A Novel Algorithmic Approach for Efficient Realization of 2-D-DCT Architecture for HEVC. - Ashish Singhadia; Pratik Bante; Indrajit Chakrabarti (IEEE Trans. Consumer Electron., 2019)

Hexagon Based Compressed Diamond Algorithm for motion estimation and its dedicated VLSI system for HD videos. - Rohan Mukherjee 002; Indubu Gaana Vinod; Indrajit Chakrabarti; Pranab Kumar Dutta; Ajoy Kumar Ray (Expert Syst. Appl., 2020)

Framework for Automated Earthquake Event Detection Based on Denoising by Adaptive Filter. - Sudipta Bose; Arijit De; Indrajit Chakrabarti (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Hardware-Efficient 2D-DCT/IDCT Architecture for Portable HEVC-Compliant Devices. - Ashish Singhadia; Meghan Mamillapalli; Indrajit Chakrabarti (IEEE Trans. Consumer Electron., 2020)

VLSI Architecture for Enhanced Approximate Message Passing Algorithm. - Kota Naga Srinivasarao Batta; Indrajit Chakrabarti (IEEE Trans. Circuits Syst. Video Technol., 2020)

Low-Complexity Interval Passing Algorithm and VLSI Architecture for Binary Compressed Sensing. - Shantharam Kalipatnapu; Indrajit Chakrabarti (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Embedding delay-based physical unclonable functions in networks-on-chip. - Prasad Nagabhushanamgari; Vikash Sehwag; Indrajit Chakrabarti; Santanu Chattopadhyay (IET Circuits Devices Syst., 2021)

High speed VLSI architecture for improved region based active contour segmentation technique. - Radhika V. Menon; Shantharam Kalipatnapu; Indrajit Chakrabarti (Integr., 2021)

Power-efficient Spike Sorting Scheme Using Analog Spiking Neural Network Classifier. - Anand Kumar Mukhopadhyay; Atul Sharma; Indrajit Chakrabarti; Arindam Basu; Mrigank Sharad (ACM J. Emerg. Technol. Comput. Syst., 2021)

Area-Delay-Power Efficient VLSI Architecture of FIR Filter for Processing Seismic Signal. - Sudipta Bose; Arijit De; Indrajit Chakrabarti (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A fast integrated deblocking filter and sample-adaptive-offset parameter estimation architecture for HEVC. - Ashish Singhadia; Md. Minhazuddin; Meghan Mamillapalli; Indrajit Chakrabarti (Microprocess. Microsystems, 2021)

Systematic realization of a fully connected deep and convolutional neural network architecture on a field programmable gate array. - Anand Kumar Mukhopadhyay; Sampurna Majumder; Indrajit Chakrabarti (Comput. Electr. Eng., 2022)

Auditory Model based Phase-Aware Bayesian Spectral Amplitude Estimator for Single-Channel Speech Enhancement. - Suman Samui; Indrajit Chakrabarti; Soumya K. Ghosh 001 (CoRR, 2022)

Efficient HEVC Encoding to Meet Bitrate and PSNR Requirements Using Parametric Modeling. - Ashish Singhadia; Preeti Samhita Pati; Chetna Singhal 001; Indrajit Chakrabarti (Circuits Syst. Signal Process., 2022)

Acoustic scene analysis using analog spiking neural network. - Anand Kumar Mukhopadhyay; Naligala Moses Prabhakar; Divya Lakshmi Duggisetty; Indrajit Chakrabarti; Mrigank Sharad (Neuromorph. Comput. Eng., 2022)

Theoretical Enumeration of Deployable Single-Output Strong PUF Instances Based on Uniformity and Uniqueness Constraints. - Venkata Sreekanth Balijabudda; Kamalesh Acharya; Rajat Subhra Chakraborty; Indrajit Chakrabarti (ICISS, 2023)

Low complexity VLSI architecture for improved primal-dual support vector machine learning core. - Radhika V. Menon; Indrajit Chakrabarti (Microprocess. Microsystems, 2023)

Design, Implementation and Characterization of a Novel Robust-by-Construction Arbiter PUF Circuit on Xilinx FPGAs. - Venkata Sreekanth Balijabudda; Indrajit Chakrabarti; Rajat Subhra Chakraborty (ATS, 2024)

Area-Delay-Power Efficient VLSI Architecture of OTFS Transceiver in Multipath Fading Channel. - Ashish Ranjan Shadangi; Suvra Sekhar Das; Indrajit Chakrabarti; B. V. Sudhakar Reddy (ICCCNT, 2024)

Practical and Efficient PUF-Based Protocol for Authentication and Key Agreement in IoT. - Sivappriya Manivannan; Rajat Subhra Chakraborty; Indrajit Chakrabarti; Jothi Rangasamy (IEEE Embed. Syst. Lett., 2024)

Low-Complexity VLSI Architecture for OTFS Transceiver Under Multipath Fading Channel. - Ashish Ranjan Shadangi; Suvra Sekhar Das; Indrajit Chakrabarti (IEEE Trans. Very Large Scale Integr. Syst., 2024)

VLSI Architecture for Implementing OTFS. - Ashish Ranjan Shadangi; Suvra Sekhar Das; Indrajit Chakrabarti (Wirel. Pers. Commun., 2024)

A Provably Secure Scheme to Prevent Master Key Recovery by Fault Attack on AES Hardware. - Sneha Swaroopa; Sivappriya Manivannan; Rajat Subhra Chakraborty; Indrajit Chakrabarti (IEEE Embed. Syst. Lett., 2024)

Accelerating U-Net: A Patchwise Memory Optimization Approach for Image Segmentation. - Chaitanya Modiboyina; Syam Babu Gundumilli; Soumya Kanti Ghosh 001; Indrajit Chakrabarti (VLSID, 2025)

A Fast Algorithm for Computation of General Integer-Order Hankel Transforms. - Amitava Ghosh; Anindya Sundar Dhar; Indrajit Chakrabarti (IEEE Signal Process. Lett., 2025)

PUFBind: PUF-Enabled Lightweight Program Binary Authentication for FPGA-based Embedded Systems. - Sneha Swaroopa; Venkata Sreekanth Balijabudda; Rajat Subhra Chakraborty; Indrajit Chakrabarti (CoRR, 2025)

Lightweight Low-Power U-Net Architecture for Semantic Segmentation. - Chaitanya Modiboyina; Indrajit Chakrabarti; Soumya K. Ghosh 001 (Circuits Syst. Signal Process., 2025)