Pulser gating: A clock gating of pulsed-latch circuits. - Sangmin Kim; Inhak Han; Seungwhun Paik; Youngsoo Shin (ASP-DAC, 2011)

Thermal signature: a simple yet accurate thermal index for floorplan optimization. - Jaeha Kung; Inhak Han; Sachin S. Sapatnekar; Youngsoo Shin (DAC, 2011)

Synthesis of clock gating logic through factored form matching. - Inhak Han; Youngsoo Shin (ICICDT, 2012)

Clock Gating Synthesis of Pulsed-Latch Circuits. - Seungwhun Paik; Inhak Han; Sangmin Kim; Youngsoo Shin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Folded circuit synthesis: Logic simplification using dual edge-triggered flip-flops. - Inhak Han; Youngsoo Shin (ICICDT, 2013)

Simplifying Clock Gating Logic by Matching Factored Forms. - Inhak Han; Youngsoo Shin (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Buffer insertion to remove hold violations at multiple process corners. - Inhak Han; Daijoon Hyun; Youngsoo Shin (ASP-DAC, 2016)

Register grouping for synthesis of clock gating logic. - Inhak Han; Jonggyu Kim; Joonhwan Yi; Youngsoo Shin (ICICDT, 2016)

Transient Clock Power Estimation of Pre-CTS Netlist. - Yonghwi Kwon 002; Jinwook Jung; Inhak Han; Youngsoo Shin (ISCAS, 2018)

Folded Circuit Synthesis: Min-Area Logic Synthesis Using Dual-Edge-Triggered Flip-Flops. - Inhak Han; Youngsoo Shin (ACM Trans. Design Autom. Electr. Syst., 2018)

Clock Gating Synthesis of Netlist with Cyclic Logic Paths. - Yonghwi Kwon 002; Inhak Han; Youngsoo Shin (ICCAD, 2019)