Stochastic implementation of the activation function for artificial neural networks. - Injune Yeo; Sang-Gyun Gi; Byung-Geun Lee; Myonglae Chu (BioCAS, 2016)

Implementation of STDP Learning for Non-volatile Memory-based Spiking Neural Network using Comparator Metastability. - Sang-Gyun Gi; Injune Yeo; Byung-Geun Lee (AICAS, 2019)

A CMOS-based Resistive Crossbar Array with Pulsed Neural Network for Deep Learning Accelerator. - Injune Yeo; Sang-Gyun Gi; Jung-Gyun Kim; Byung-Geun Lee (AICAS, 2019)

A Power and Area Efficient CMOS Stochastic Neuron for Neural Networks Employing Resistive Crossbar Array. - Injune Yeo; Myonglae Chu; Byung-Geun Lee (IEEE Trans. Biomed. Circuits Syst., 2019)

A Hardware and Energy-Efficient Online Learning Neural Network With an RRAM Crossbar Array and Stochastic Neurons. - Injune Yeo; Sang-Gyun Gi; Gunuk Wang; Byung-Geun Lee (IEEE Trans. Ind. Electron., 2021)

A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification. - Shreyas Kolala Venkataramanaiah; Jian Meng; Han-Sok Suh; Injune Yeo; Jyotishman Saikia; Sai Kiran Cherupally; Yichi Zhang 006; Zhiru Zhang; Jae-sun Seo (ESSCIRC, 2022)

Sparse and Robust RRAM-based Efficient In-memory Computing for DNN Inference. - Jian Meng; Injune Yeo; Wonbo Shim; Li Yang 009; Deliang Fan; Shimeng Yu; Jae-Sun Seo (IRPS, 2022)

Temperature-Resilient RRAM-Based In-Memory Computing for DNN Inference. - Jian Meng; Wonbo Shim; Li Yang 009; Injune Yeo; Deliang Fan; Shimeng Yu; Jae-sun Seo (IEEE Micro, 2022)

Hybrid RRAM/SRAM in-Memory Computing for Robust DNN Acceleration. - Gokul Krishnan; Zhenyu Wang; Injune Yeo; Li Yang 009; Jian Meng; Maximilian Liehr; Rajiv V. Joshi; Nathaniel C. Cady; Deliang Fan; Jae-Sun Seo; Yu Cao 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

3D-ISC: A 65nm 3D Compatible In-Sensor Computing Accelerator with Reconfigurable Tile Architecture for Real-Time DVS Data Compression. - Gokul Krishnan; Gopikrishnan Raveendran Nair; Jonghyun Oh; Anupreetham Anupreetham; Pragnya Sudershan Nalla; Ahmed Hassan; Injune Yeo; Kishore Kasichainula; Jae-sun Seo; Mingoo Seok; Yu Cao 001 (A-SSCC, 2023)

A 92 F2 / bit Physically Unclonable Function Exploiting Channel Charge Injection and Mismatch Accumulation. - Injune Yeo; Dong-Woo Jee; Jae-Sun Seo (CICC, 2023)

A Time-Memory-based CMOS Vision Sensor with In-Pixel Temporal Derivative Computing for Multi-Mode Image Processing. - Dong-Woo Jee; Seong-Min Ko; Kishore Kasichainula; Injune Yeo; Yu Cao 001; Jae-Sun Seo (ESSCIRC, 2023)

FP-IMC: A 28nm All-Digital Configurable Floating-Point In-Memory Computing Macro. - Jyotishman Saikia; Amitesh Sridharan; Injune Yeo; Shreyas K. Venkataramanaiah; Deliang Fan; Jae-Sun Seo (ESSCIRC, 2023)

A 65nm RRAM Compute-in-Memory Macro for Genome Sequencing Alignment. - Fan Zhang 069; Wangxin He; Injune Yeo; Maximilian Liehr; Nathaniel C. Cady; Yu Cao 001; Jae-Sun Seo; Deliang Fan (ESSCIRC, 2023)

Improving the Efficiency of CMOS Image Sensors through In-Sensor Selective Attention. - Tianyi Zhang; Kishore Kasichainula; Dong-Woo Jee; Injune Yeo; Yaoxin Zhuo; Baoxin Li; Jae-sun Seo; Yu Cao 001 (ISCAS, 2023)

A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity. - Shreyas Kolala Venkataramanaiah; Jian Meng; Han-Sok Suh; Injune Yeo; Jyotishman Saikia; Sai Kiran Cherupally; Yichi Zhang 006; Zhiru Zhang; Jae-Sun Seo (IEEE J. Solid State Circuits, 2023)

A 65-nm RRAM Compute-in-Memory Macro for Genome Processing. - Fan Zhang 069; Amitesh Sridharan; Wangxin He; Injune Yeo; Maximilian Liehr; Wei Zhang 076; Nathaniel C. Cady; Yu Cao 001; Jae-Sun Seo; Deliang Fan (IEEE J. Solid State Circuits, 2024)

Analysis of Pixel Noise in Dynamic Vision Sensors. - Donghwan Seo; Jung-Gyun Kim; Injune Yeo; Hyunkeun Lee; Byung-Geun Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)