Inna Partin-Vaisband

Orcid: 0000-0002-6399-6672

According to our database1, Inna Partin-Vaisband authored at least 29 papers between 2009 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
Multiterminal Pathfinding in Practical VLSI Systems with Deep Neural Networks.
ACM Trans. Design Autom. Electr. Syst., July, 2023

Vertical Power Delivery for Emerging Packaging and Integration Platforms - Power Conversion and Distribution.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

2022
NoD: A Neural Network-Over-Decoder for Edge Intelligence.
IEEE Trans. Very Large Scale Integr. Syst., 2022

A Machine Learning Pipeline Stage for Adaptive Frequency Adjustment.
IEEE Trans. Computers, 2022

Knowledge Graph Embedding and Visualization for Pre-Silicon Detection of Hardware Trojans.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Guest Editorial Cross-Layer Designs, Methodologies, and Systems to Enable Micro AI for On-Device Intelligence.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

A Single-MOSFET Analog High Resolution-Targeted (SMART) Multiplier for Machine Learning Classification.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

PySyn: A Rapid Synthesis for Mixed-Signal Machine Learning Classification.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

Late Breaking Results: Parallelizing Net Routing with cGANs.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Real-Time Detection of Power Analysis Attacks by Machine Learning of Power Supply Variations On-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Unified Learning Platform for Dynamic Frequency Scaling in Pipelined Processors.
CoRR, 2020

Late Breaking Results: A Neural Network that Routes ICs.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Leveraging Independent Double-Gate FinFET Devices for Machine Learning Classification.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Exploiting Machine Learning Against On-Chip Power Analysis Attacks: Tradeoffs and Design Considerations.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Progressive VAE Training on Highly Sparse and Imbalanced Data.
CoRR, 2019

Exploiting Dual-Gate Ambipolar CNFETs for Scalable Machine Learning Classification.
CoRR, 2019

A Single-MOSFET MAC for Confidence and Resolution (CORE) Driven Machine Learning Classification.
CoRR, 2019

Security Network On-Chip for Mitigating Side-Channel Attacks.
Proceedings of the 21st ACM/IEEE International Workshop on System Level Interconnect Prediction, 2019

2018
Efficient Wireless Power Transfer for Heterogeneous Adaptive IoT Systems.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2017
Automated Design of Stable Power Delivery Systems for Heterogeneous IoT Systems.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2015
A Closed-Loop Reconfigurable Switched-Capacitor DC-DC Converter for Sub-mW Energy Harvesting Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Energy efficient adaptive clustering of on-chip power delivery systems.
Integr., 2015

2014
Digitally Controlled Pulse Width Modulator for On-Chip Power Management.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Power network-on-chip for scalable power delivery.
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2014

Dynamic power management with power network-on-chip.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Computationally efficient clustering of power supplies in heterogeneous real time systems.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Digitally controlled wide range pulse width modulator for on-chip power supplies.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Energy metrics for power efficient crosslink and mesh topologies.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2009
Power efficient tree-based crosslinks for skew reduction.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009


  Loading...