Register allocation for high-level synthesis using dual supply voltages. - Insup Shin; Seungwhun Paik; Youngsoo Shin (DAC, 2009)

HLS-l: High-level synthesis of high performance latch-based circuits. - Seungwhun Paik; Insup Shin; Youngsoo Shin (DATE, 2009)

Synthesis and implementation of active mode power gating circuits. - Jun Seomun; Insup Shin; Youngsoo Shin (DAC, 2010)

HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures. - Seungwhun Paik; Insup Shin; Taewhan Kim; Youngsoo Shin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Selectively patterned masks: Structured ASIC with asymptotically ASIC performance. - Donkyu Baek; Insup Shin; Seungwhun Paik; Youngsoo Shin (ASP-DAC, 2011)

Introducing irregularity to routing architecture of structured ASIC for better routability. - Insup Shin; Donkyu Baek; Youngsoo Shin (FPT, 2012)

Gate delay modeling for static timing analysis of body-biased circuits. - Donkyu Baek; Insup Shin; Youngsoo Shin (ICICDT, 2012)

Synthesis of Active-Mode Power-Gating Circuits. - Jun Seomun; Insup Shin; Youngsoo Shin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures. - Insup Shin; Seungwhun Paik; Dongwan Shin; Youngsoo Shin (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A pipeline architecture with 1-cycle timing error correction for low voltage operations. - Insup Shin; Jae-Joon Kim; Yu-Shiang Lin; Youngsoo Shin (ISLPED, 2013)

Accurate gate delay Extraction for Timing Analysis of Body-Biased Circuits. - Donkyu Baek; Insup Shin; Youngsoo Shin (J. Circuits Syst. Comput., 2013)

Power minimization of pipeline architecture through 1-cycle error correction and voltage scaling. - Insup Shin; Jae-Joon Kim; Youngsoo Shin (ASP-DAC, 2014)

HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning. - Youngsoo Shin; Insup Shin; Donkyu Baek; Duckhwan Kim 001; Seungwhun Paik (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Aggressive Voltage Scaling Through Fast Correction of Multiple Errors With Seamless Pipeline Operation. - Insup Shin; Jae-Joon Kim; Youngsoo Shin (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements. - Insup Shin; Jae-Joon Kim; Yu-Shiang Lin; Youngsoo Shin (IEEE Trans. Very Large Scale Integr. Syst., 2016)