A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme. - Kyomin Sohn; Taesik Na; Indal Song; Yong Shim; Wonil Bae; Sanghee Kang; Dongsu Lee; Hangyun Jung; Hanki Jeoung; Ki Won Lee; Junsuk Park; Jongeun Lee; et al. (ISSCC, 2012)

A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme. - Kyomin Sohn; Taesik Na; Indal Song; Yong Shim; Wonil Bae; Sanghee Kang; Dongsu Lee; Hangyun Jung; Seok-Hun Hyun; Hanki Jeoung; Ki Won Lee; Jun-Seok Park; et al. (IEEE J. Solid State Circuits, 2013)

30.3 A 24Gb 42.5Gb/s GDDR7 DRAM with Low-Power WCK Distribution, an RC-Optimized Dual-Emphasis TX, and Voltage/Time-Margin-Enhanced Power Reduction. - Sang-Hoon Kim; Jaehyeok Baek; Moon-Chul Choi; Daewoong Lee; Donggun An; Se-Mi Kim; Yeonggeun Song; Minkyo Shim; Sung-Yong Cho; Dongha Lee; Gun-hee Cho; Inwoo Jun; et al. (ISSCC, 2025)