Bandwidth-to-area comparison of through silicon vias and inductive links for 3-D ICs. - Ioannis A. Papistas; Vasilis F. Pavlidis (ECCTD, 2015)

Inter-Tier Crosstalk Noise On Power Delivery Networks For 3-D ICs With Inductively-Coupled Interconnects. - Ioannis A. Papistas; Vasilis F. Pavlidis (ACM Great Lakes Symposium on VLSI, 2016)

Crosstalk noise effects of on-chip inductive links on power delivery networks. - Ioannis A. Papistas; Vasilis F. Pavlidis (ISCAS, 2016)

Contactless inter-tier communication for heterogeneous 3-D ICs. - Ioannis A. Papistas; Vasilis F. Pavlidis (ISCAS, 2017)

Contactless Heterogeneous 3-D ICs for Smart Sensing Systems. - Ioannis A. Papistas; Vasilis F. Pavlidis (Integr., 2018)

Efficient Modeling of Crosstalk Noise on Power Distribution Networks for Contactless 3-D ICs. - Ioannis A. Papistas; Vasilis F. Pavlidis (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Design methodologies for heterogeneous 3-D integrated systems. - Ioannis A. Papistas (2018)

FQ-Conv: Fully Quantized Convolution for Efficient and Accurate Inference. - Bram-Ernst Verhoef; Nathan Laubeuf; Stefan Cosemans; Peter Debacker; Ioannis A. Papistas; Arindam Mallik; Diederik Verkest (CoRR, 2019)

Fabrication Cost Analysis for Contactless 3-D ICs. - Ioannis A. Papistas; Vasilis F. Pavlidis; Dimitrios Velenis (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Cost Modeling and Analysis of TSV and Contactless 3D-ICs. - Minmin Jiang; Ioannis A. Papistas; Vasilis F. Pavlidis (ACM Great Lakes Symposium on VLSI, 2020)

A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm2 in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration. - Ioannis A. Papistas; Stefan Cosemans; Bram Rooseleer; Jonas Doevenspeck; Myung Hee Na; Arindam Mallik; Peter Debacker; Diederik Verkest (CICC, 2021)

Design-Technology Space Exploration for Energy Efficient AiMC-Based Inference Acceleration. - Debjyoti Bhattacharjee; Nathan Laubeuf; Stefan Cosemans; Ioannis A. Papistas; Arindam Mallik; Peter Debacker; Myung Hee Na; Diederik Verkest (ISCAS, 2021)

Charge Sharing and Charge Injection A/D Converters for Analog In-Memory Computing. - Michele Caselli; Ioannis A. Papistas; Stefan Cosemans; Arindam Mallik; Peter Debacker; Diederik Verkest (NEWCAS, 2021)

DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC. - Kodai Ueyoshi; Ioannis A. Papistas; Pouya Houshmand; Giuseppe Maria Sarda; Vikram Jain; Man Shi; Qilin Zheng; Juan Sebastian Piedrahita Giraldo; Peter Vrancx; Jonas Doevenspeck; Debjyoti Bhattacharjee; Stefan Cosemans; et al. (ISSCC, 2022)

Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration. - Nathan Laubeuf; Jonas Doevenspeck; Ioannis A. Papistas; Michele Caselli; Stefan Cosemans; Peter Vrancx; Debjyoti Bhattacharjee; Arindam Mallik; Peter Debacker; Diederik Verkest; Francky Catthoor; Rudy Lauwereins (ACM Trans. Design Autom. Electr. Syst., 2022)

DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge. - Pouya Houshmand; Giuseppe Maria Sarda; Vikram Jain; Kodai Ueyoshi; Ioannis A. Papistas; Man Shi; Qilin Zheng; Debjyoti Bhattacharjee; Arindam Mallik; Peter Debacker; Diederik Verkest; Marian Verhelst (IEEE J. Solid State Circuits, 2023)

11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge. - Pascal Alexander Hager; Bert Moons; Stefan Cosemans; Ioannis A. Papistas; Bram Rooseleer; Jeroen Van Loon; Roel Uytterhoeven; Florian Zaruba; Spyridoula Koumousi; Milos Stanisavljevic; Stefan Mach; Sebastiaan Mutsaards; et al. (ISSCC, 2024)